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Home > Level 2 Memory Interface > STRT instructions |
Take particular care with noncacheable write accesses when
using the STRT
instruction. To put the correct information
on the external bus ensure one of the following:
The access is to Strongly-ordered memory.
This ensures that the STRT
instruction does not
merge in the store buffer.
The access is to Device memory.
This ensures that the STRT
instruction does not
merge in the store buffer.
A DSB
instruction is issued before
the STRT
and after the STRT
.
This prevents an STRT
from merging into an existing
slot at the same 64-bit address, or merging with another write at
the same 64-bit address.
Table 7.6 shows Cortex-A9 modes and corresponding AxPROT values.
Table 7.6. Cortex-A9 mode and AxPROT values
Processor mode | Type of access | Value of AxPROT |
---|---|---|
User | Cacheable read access | User |
Privileged | Privileged | |
User | Noncacheable read access | User |
Privileged | Privileged | |
- | Cacheable write access | Always marked as Privileged |
User | Noncacheable write access | User |
Privileged | Noncacheable write access | Privileged, except when using |