7.3. STRT instructions

Take particular care with noncacheable write accesses when using the STRT instruction. To put the correct information on the external bus ensure one of the following:

Table 7.6 shows Cortex-A9 modes and corresponding AxPROT values.

Table 7.6. Cortex-A9 mode and AxPROT values

Processor modeType of accessValue of AxPROT
UserCacheable read accessUser
PrivilegedPrivileged
UserNoncacheable read accessUser
PrivilegedPrivileged
-Cacheable write accessAlways marked as Privileged
UserNoncacheable write accessUser
PrivilegedNoncacheable write access

Privileged, except when using STRT


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