5.1.1. Memory Management Unit

The MMU performs the following operations:

Page sizes

The Cortex-A9 processor supports the following page sizes:

  • 16MB supersections

    The processor supports supersections that consist of 16MB blocks of memory. The processor does not support the optional extension of physical address bits [39:32].

  • 1MB sections

  • 64KB large pages

  • 4KB small pages.


Sixteen access domains are supported.


A two-level TLB structure is implemented. Four entries in the main TLB are lockable.


TLB entries can be global, or can be associated with particular processes or applications using ASIDs. ASIDs enable TLB entries to remain resident during context switches, avoiding the requirement of reloading them subsequently.

System control coprocessor

TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated within the core. This coprocessor provides a standard mechanism for configuring the level one memory system.

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