6.3. About the L1 instruction side memory system

The L1 instruction side memory system is responsible for providing an instruction stream to the Cortex-A9 processor. To increase overall performance and to reduce power consumption, it contains the following functionality:

Figure 6.1 shows this.

Figure 6.1. Branch prediction and instruction cache

The ISide comprises the following:

The Prefetch Unit (PFU)

The Prefetch Unit implements a two-level prediction mechanism, comprising:

  • a two-way BTAC of 512 entries organized as two-way x 256 entries implemented in RAMs.

  • a Global History Buffer (GHB) containing 4096 2-bit predictors implemented in RAMs

  • a return stack with eight 32-bit entries.

    The prediction scheme is available in ARM state, Thumb state, ThumbEE state, and Jazelle state. It is also capable of predicting state changes from ARM to Thumb, and from Thumb to ARM. It does not predict any other state changes. Nor does it predict any instruction that changes the mode of the core. See Program flow prediction.

Instruction Cache Controller

The instruction cache controller fetches the instructions from memory depending on the program flow predicted by the prefetch unit.

The instruction cache is 4-way set associative. It comprises the following features:

  • configurable sizes of 16KB, 32KB, or 64KB

  • Virtually Indexed Physically Tagged (VIPT)

  • 64-bit native accesses so as to provide up to four instructions per cycle to the prefetch unit

  • security extensions support

  • no lockdown support.

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