2.5.2. Power-on reset

You must apply power-on or cold reset to the Cortex-A9 processor when power is first applied to the system. In the case of power-on reset, the leading edge, that is the falling edge, of the reset signals do not have to be synchronous to CLK, but the rising edge must be.

You must assert the reset signals for at least nine CLK cycles to ensure correct reset behavior.

On power-on, perform the following reset sequence:

  1. Apply all resets.

  2. Apply at least 9 CLK cycles, plus at least one cycle in each other clock domain, or more if the documentation for other components requires it. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by for example applying 15 cycles on every clock domain.

  3. Stop the CLK clock. If there is a Data Engine present, use NEONCLKOFF. See Configuration signals.

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release resets.

  6. Wait for the equivalent of another approximately 10 cycles, again to compensate for clock and reset tree latencies.

  7. Restart the clock.

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