A.11. MBIST interface

Table A.21 shows the MBIST interface signals. These signals are present only when the BIST interface is present.

Table A.21. MBIST interface signals

NameI/OSourceDescription
MBISTADDR[10:0]IMBIST controller

MBIST address bus.

MBISTARRAY[19:0]IMBIST arrays used for testing RAMs.
MBISTENABLEI

MBIST test enable

MBISTWRITEEN

IGlobal write enable.

MBISTREADEN

IGlobal read enable.

The size of some MBIST signals depends on whether the implementation has parity support or not. Table A.22 shows these signals with parity support implemented.

Table A.22. MBIST signals with parity support implemented

NameI/OSource or destinationDescription
MBISTBE[32:0]IMBIST controllerMBIST write enable
MBISTINDATA[71:0]IMBIST data in
MBISTOUTDATA[71:0]OMBIST data out

Table A.23 shows these signals without parity support implemented.

Table A.23. MBIST signals without parity support implemented

NameI/OSource/DestinationDescription
MBISTBE[25:0]IMBIST controllerMBIST write enable
MBISTINDATA[63:0]IMBIST data in
MBISTOUTDATA[63:0]OMBIST data out

See the Cortex-A9 r0p0 MBIST TRM for a description of MBIST.

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