A.13.2. APB interface signals

Table A.26 shows the APB interface signals.

Table A.26. APB interface signals

NameI/OSource or destinationDescription
PENABLEDBGICoreSight APB devicesAPB clock enable.
PRDATADBG[31:0]OAPB read data bus.
PSELDBGI

Debug registers select:

0 = debug registers not selected

1 = debug registers selected.

PSLVERRDBGOAPB slave error signal.
PWRITEDBGI APB Read/Write signal.
PADDRDBG[12:2]I

Programming address.

PADDRDBG31I

APB address bus bit [31]:

0 = not an external debugger access

1 = external debugger access.

PREADYDBGO

APB slave ready. An APB slave can assert PREADY to extend a transfer.

PWDATADBG[31:0]IAPB write data.

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