Cortex-A9 Technical Reference Manual: A.13.2. APB interface signals

Table A.26 shows the APB interface signals.

Table A.26. APB interface signals

Name	I/O	Source or destination	Description
PENABLEDBG	I	CoreSight APB devices	APB clock enable.
PRDATADBG[31:0]	O		APB read data bus.
PSELDBG	I		Debug registers select: 0 = debug registers not selected 1 = debug registers selected.
PSLVERRDBG	O		APB slave error signal.
PWRITEDBG	I		APB Read/Write signal.
PADDRDBG[12:2]	I		Programming address.
PADDRDBG31	I		APB address bus bit [31]: 0 = not an external debugger access 1 = external debugger access.
PREADYDBG	O		APB slave ready. An APB slave can assert PREADY to extend a transfer.
PWDATADBG[31:0]	I		APB write data.

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