Cortex-A9 Technical Reference Manual: A.8. Performance monitoring signals

A.8. Performance monitoring signals

Table A.17 shows the performance monitoring signals.

Table A.17. Performance monitoring signals

Name	I/O	Destination	Description
PMUEVENT[57:0]	O	PTM or external monitoring unit	Performance Monitoring Unit event bus. See Table A.18.
PMUIRQ	O		Performance Monitoring Unit interrupt signal.
PMUSECURE	O		Gives the status of the Cortex-A9 processor 0 = in Non-secure state 1 = in Secure state. This signal does not provide input to CoreSight Trace delivery infrastructure.
PMUPRIV	O		Gives the status of the Cortex-A9 processor 0 = in user mode 1 = in privileged mode. This signal does not provide input to CoreSight Trace delivery infrastructure.

Table A.18 gives the correlation between PMUEVENT signals and their event numbers.

Table A.18. Event signals and event numbers

Name	Event number	Description
PMUEVENT[0]	`0x00`	Software increment
PMUEVENT[1]	`0x01`	Instruction cache miss
PMUEVENT[2]	`0x02`	Instruction micro TLB miss
PMUEVENT[3]	`0x03`	Data cache miss
PMUEVENT[4]	`0x04`	Data cache access
PMUEVENT[5]	`0x05`	Data micro TLB miss
PMUEVENT[6]	`0x06`	Data read
PMUEVENT[7]	`0x07`	Data writes
-	`0x08`	Unused^[a]
PMUEVENT[8]	`0x68`	b00 no instructions renamed b01 one instruction renamed b10 two instructions renamed.
PMUEVENT[9]	`0x68`
PMUEVENT[10]	`0x09`	Exception taken
PMUEVENT[11]	`0x0A`	Exception returns
PMUEVENT[12]	`0x0B`	Write context id
PMUEVENT[13]	`0x0C`	Software change of PC
PMUEVENT[14]	`0x0D`	Immediate branch
-	`0x0E`	Unused^[b]
PMUEVENT[15]	`0x6E`	Predictable function return^b
PMUEVENT[16]	`0x0F`	Unaligned
PMUEVENT[17]	`0x10`	Branch mispredicted or not predicted
Not exported	`0x11`	Cycle count
PMUEVENT[18]	`0x12`	Predictable branches
PMUEVENT[19]	`0x40`	Java bytecode
PMUEVENT[20]	`0x41`	Software Java bytecode
PMUEVENT[21]	`0x42`	Jazelle backward branch
PMUEVENT[22]	`0x50`	Coherent linefill miss^[c]
PMUEVENT[23]	`0x51`	Coherent linefill hit^c
PMUEVENT[24]	`0x60`	Instruction cache dependent stall
PMUEVENT[25]	`0x61`	Data cache dependent stall
PMUEVENT[26]	`0x62`	Main TLB miss stall
PMUEVENT[27]	`0x63`	STREX passed
PMUEVENT[28]	`0x64`	STREX failed
PMUEVENT[29]	`0x65`	Data eviction
PMUEVENT[30]	`0x66`	Issue does not dispatch any instruction
PMUEVENT[31]	`0x67`	Issue is empty
PMUEVENT[32]	`0x70`	Main Execution Unit pipe
PMUEVENT[33]	`0x71`	Second Execution Unit pipe
PMUEVENT[34]	`0x72`	Load/Store pipe
PMUEVENT[35]	`0x73`	b00 no floating-point instruction renamed b01 one floating-point instruction renamed b10 two floating-point instructions renamed
PMUEVENT[36]	`0x73`
PMUEVENT[37]	0x74	b00 no NEON instruction renamed b01 one NEON instruction renamed b10 two NEON instructions renamed
PMUEVENT[38]	0x74
PMUEVENT[39]	`0x80`	PLD stall
PMUEVENT[40]	`0x81`	Write stall
PMUEVENT[41]	`0x82`	Instruction main TLB miss stall
PMUEVENT[42]	`0x83`	Data main TLB miss stall
PMUEVENT[43]	`0x84`	Instruction micro TLB miss stall
PMUEVENT[44]	`0x85`	Data micro TLB miss stall
PMUEVENT[45]	`0x86`	DMB stall
PMUEVENT[46]	`0x8A`	Integer core clock disabled
PMUEVENT[47]	`0x8B`	Data Engine clock disabled
PMUEVENT[48]	`0x90`	ISB
PMUEVENT[49]	`0x91`	DSB
PMUEVENT[50]	`0x92`	DMB
PMUEVENT[51]	`0x93`	External interrupt
PMUEVENT[52]	0xA0	PLE cache line request completed
PMUEVENT[53]	0xA1	PLE cache line request skipped
PMUEVENT[54]	0xA2	PLE FIFO Flush
PMUEVENT[55]	0xA3	PLE request completed
PMUEVENT[56]	0xA4	PLE FIFO Overflow
PMUEVENT[57]	0xA5	PLE request programmed
^[a]Not generated by Cortex-A9 processors. Replaced by the similar event `0x68`. ^[b]Not generated by Cortex-A9 processors. Replaced by the similar event `0x6E`. ^[c]Used in multiprocessor configurations

See Table 9.2.

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