4.2. Summary of system control coprocessor registers

This section shows summary tables of the register allocation and reset values of the system control coprocessor where:

All system control coprocessor registers are 32 bits wide, except for the Program New Channel operation described in PLE Program New Channel operation. Reserved register addresses are RAZ/WI.

This section does not reproduce information about registers already described in the ARM Architecture Reference Manual. This chapter describes the implementation-defined control coprocessor registers.

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E