6.1. About the L1 memory system

The L1 memory system has:

The data side of the L1 memory system has:


You must invalidate the instruction cache, the data cache, and BTAC before using them. You are not required to invalidate the main TLB, even though it is recommended for safety reasons. This ensures compatibility with future revisions of the processor.

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E