2.3.1. Synchronous clocking

The Cortex-A9 processor does not have any asynchronous interfaces. All the bus interfaces and the interrupt signals must be synchronous with reference to CLK.

The AXI bus clock domain can be run at n:1 (AXI: processor ratio to CLK) using the ACLKEN signal.

Figure 2.3 shows a timing example with ACKLENM0 used with a 3:1 clock ratio between CLK and ACLK.

Figure 2.3. ACLKENM0 used with a 3:1 clock ratio

The master port, Master0, changes the AXI outputs only on the CLK rising edge when ACLKENM0 is HIGH.

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