Cortex-A9 Technical Reference Manual: 10.2.1. Debug register access

10.2.1. Debug register access

You can access the debug registers:

through the cp14 interface. The debug registers are mapped to coprocessor instructions.
through the APB using the relevant offset, with the following exceptions:
- DBGRAR
- DBGSAR
- DBGSCR-int
- DBGTR-int.

External views of DBSCR and DBGTR are accessible through memory-mapped APB access.

Table 10.1 shows the CP14 interface registers. All other registers are described in the ARM Architecture Reference Manual.

Table 10.1. CP14 interface registers

Register number	Offset	CP14 instruction	Access	Register name	Description
0	`0x000`	`0 c0 c0 0`	RO	DBGDIDR^[a]	- ^[b]
-	-	`0 c1 c0 0`	RO	DBGDRAR^a	-
-	-	`0 c2 c0 0`	RO	DBGDSAR^a	-
-	-	`0 c0 c1 0`	RO	DBGDSCR-int^a^b	-
-	-	`0 c0 c5 0`	RW	DBGTR^a	-
1-5	-	-	-	Reserved	-
6	`0x018`	`0 c0 c6 0`	RW	DBGWFAR	-
7	`0x01C`	`0 c0 c7 0`	RW	DBGVCR	-
8	-	-	-	Reserved	-
9	`0x024`	`0 c0 c9 0`	RAZ/WI	DBGECR	Not implemented
10	`0x028`	`0 c0 c10 0`	RAZ/WI	DBGDSCCR	Debug State Cache Control Register (DBGDSCCR)
11	`0x02C`	`0 c0 c11 0`	RAZ/WI	DBGDSMCR	Not implemented
12-31	-	-	-	Reserved	-
32	`0x080`	`0 c0 c0 2`	RW	DBGDTRRX -ext	-
33	`0x084`	`0 c0 c1 2`	WO	DBGITR	-
33	`0x084`	`0 c0 c1 2`	RO	DBGPCSR	-
34	`0x088`	`0 c0 c2 2`	RW	DBGDSCR-ext	-
35	`0x08C`	`0 c0 c3 2`	RW	DBGDTRTX-ext	-
36	`0x090`	`0 c0 c4 2`	WO	DBGDRCR	-
37-63	-	-	-	Reserved	-
64-79	`0x100`-`0x13C`	`0 c0 c0 15 4`	RW	DBGBVRn	Breakpoint Value Registers
80-95	`0x140`-`0x17C`	`0 c0 c0 15 5`	RW	DBGBCRn	Breakpoint Control Registers
96-111	`0x180`-`0x1BC`	`0 c0 c0 15 6`	RW	DBGWVRn	Watchpoint Value Registers
112-127	`0x1C0`-`0x1FC`	`0 c0 c0 15 7`	RW	DBGWCRn	Watchpoint Control Registers
128-191	-	-	-	Reserved	-
192	`0x300`	`0 c1 c0 4`	RAZ/WI	DBGOSLAR	Not implemented
193	`0x304`	`0 c1 c1 4`	RAZ/WI	DBGOSLSR	Not implemented
194	`0x308`	`0 c1 c2 4`	RAZ/WI	DBGOSSRR	Not implemented
195	-	-	-	Reserved	-
196	`0x310`	`0 c1 c4 4`	RO	DBGPRCR	-
197	`0x314`	`0 c1 c5 4`	RO	DBGPRSR	-
198-511	-	-	-	Reserved	-
512-575	`0x800`-`0x8FC`	-	-	-	PMU registers^[c]
576-831	-	-	-	Reserved	-
832-895	`0xD00`-`0xDFC`	`0 c6 c0 15 4-7`	RW	Unpredictable	-
896-927	-	-		Reserved	-
928-959	`0xE80`-`0xEFC0`	`0 c7 c0 15 2-3`	RAZ/WI	-	-
960	`0xF00`	`0 c7 c0 4`	RAZ/WI	DBGITCTRL	Integration Mode Control Register
961-999	`0xF04`-`0xF9C`	-	-	-	-
1000	`0xFA0`	`0 c7 c8 6`	RW	DBGCLAIMSET	Claim Tag Set Register
1001	`0xFA4`	`0 c7 c9 6`	RW	DBGCLAIMCLR	Claim Tag Clear Register
1002-1003	-	-	-	Reserved	-
1004	`0xFB0`	`0 c7 c12 6`	WO	DBGLAR	Lock Access Register
1005	`0xFB4`	`0 c7 c13 6`	RO	DBGLSR	Lock Status Register
1006	`0xFB8`	`0 c7 c14 6`	RO	DBGAUTHSTATUS	Authentication Status Register
1007-1009	-	-	-	Reserved	-
1010	`0xFC8`	`0 c7 c2 7`	RAZ	DBGDEVID	-
1011	`0xFCC`	`0 c7 c3 7`	RO	DBGDEVTYPE	Device Type Register
1012-1016	`0xFD0`-`0xFEC`	`0 c7 c4-8 7`	RO	PERIPHERALID	Identification Registers
1017-1019	-	-	-	Reserved	-
1020-1023	`0xFF0`-`0xFFC`	`0 c7 c12-15 7`	RO	COMPONENTID	Identification Registers
^[a]Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface. ^[b]Accessible in User mode if bit[12] of the DBGSCR is clear. Also accessible in privileged modes. ^[c]PMU registers are part of the CP15 interface. Reads from the extended CP14 interface return zero. See c9 summary table. See also Chapter 9 Performance Monitoring Unit.

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