10.2.1. Debug register access

You can access the debug registers:

External views of DBSCR and DBGTR are accessible through memory-mapped APB access.

Table 10.1 shows the CP14 interface registers. All other registers are described in the ARM Architecture Reference Manual.

Table 10.1. CP14 interface registers

Register number Offset CP14 instruction Access Register name Description
00x0000 c0 c0 0 RO

DBGDIDR[a]

-

[b]

-- 0 c1 c0 0 RO DBGDRARa-
-- 0 c2 c0 0 RO

DBGDSARa

-
-- 0 c0 c1 0 RO

DBGDSCR-intab

-
-- 0 c0 c5 0 RW

DBGTRa

-
1-5---Reserved-
6 0x018 0 c0 c6 0 RW DBGWFAR -
7 0x01C 0 c0 c7 0 RW DBGVCR -
8 ---Reserved -
9 0x024 0 c0 c9 0 RAZ/WIDBGECR Not implemented
10 0x028 0 c0 c10 0 RAZ/WIDBGDSCCR Debug State Cache Control Register (DBGDSCCR)
11 0x02C0 c0 c11 0 RAZ/WIDBGDSMCR Not implemented
12-31 ---Reserved -
32 0x080 0 c0 c0 2 RW DBGDTRRX -ext-
33 0x084 0 c0 c1 2WO DBGITR -
33 0x0840 c0 c1 2 RO DBGPCSR -
34 0x0880 c0 c2 2 RW DBGDSCR-ext-
35 0x08C0 c0 c3 2 RW DBGDTRTX-ext-
36 0x0900 c0 c4 2 WO DBGDRCR -
37-63 ---Reserved -
64-79

0x100-0x13C

0 c0 c0 15 4RW DBGBVRn Breakpoint Value Registers
80-95

0x140-0x17C

0 c0 c0 15 5RW DBGBCRn Breakpoint Control Registers
96-111

0x180-0x1BC

0 c0 c0 15 6RW DBGWVRn Watchpoint Value Registers
112-127

0x1C0-0x1FC

0 c0 c0 15 7 RW DBGWCRn Watchpoint Control Registers
128-191 ---Reserved -
192 0x3000 c1 c0 4 RAZ/WI DBGOSLAR Not implemented
193 0x3040 c1 c1 4RAZ/WIDBGOSLSR Not implemented
194 0x3080 c1 c2 4RAZ/WI DBGOSSRRNot implemented
195 ---Reserved -
196 0x3100 c1 c4 4 RO DBGPRCR -
197 0x3140 c1 c5 4 RO DBGPRSR -
198-511 ---Reserved -
512-575

0x800-0x8FC

---

PMU registers[c]

576-831 ---Reserved -
832-895

0xD00-0xDFC

0 c6 c0 15 4-7RW Unpredictable -
896-927 -- Reserved -
928-959

0xE80-0xEFC0

0 c7 c0 15 2-3RAZ/WI--
9600xF00 0 c7 c0 4RAZ/WI DBGITCTRLIntegration Mode Control Register
961-999

0xF04-0xF9C

--- -
10000xFA00 c7 c8 6RWDBGCLAIMSETClaim Tag Set Register
10010xFA40 c7 c9 6RWDBGCLAIMCLRClaim Tag Clear Register
1002-1003---Reserved-
1004 0xFB00 c7 c12 6WODBGLARLock Access Register
1005 0xFB40 c7 c13 6RODBGLSRLock Status Register
10060xFB80 c7 c14 6RODBGAUTHSTATUSAuthentication Status Register
1007-1009---Reserved-
10100xFC80 c7 c2 7RAZDBGDEVID-
10110xFCC0 c7 c3 7RODBGDEVTYPEDevice Type Register
1012-1016

0xFD0-0xFEC

0 c7 c4-8 7ROPERIPHERALIDIdentification Registers
1017-1019---Reserved-
1020-1023

0xFF0-0xFFC

0 c7 c12-15 7ROCOMPONENTIDIdentification Registers

[a] Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface.

[b] Accessible in User mode if bit[12] of the DBGSCR is clear. Also accessible in privileged modes.

[c] PMU registers are part of the CP15 interface. Reads from the extended CP14 interface return zero. See c9 summary table. See also Chapter 9 Performance Monitoring Unit.


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