Cortex™-A9 Technical Reference Manual

Revision: r2p0

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Timing diagrams
Additional reading
ARM publications
Other publications
Feedback on this product
Feedback on this book
1. Introduction
1.1. About the Cortex-A9 processor
1.1.1. Data Engine
1.1.2. System design components
1.2. Cortex-A9 variants
1.3. Compliance
1.4. Features
1.5. Interfaces
1.6. Configurable options for the Cortex-A9 processor
1.7. Test features
1.8. Product documentation, design flow, and architecture
1.8.1. Documentation
1.8.2. Design flow
1.8.3. Architecture and protocol information
1.9. Product revisions
1.9.1. Differences in functionality between r0p0 and r0p1
1.9.2. Differences in functionality between r0p1 and r1p0
1.9.3. Differences in functionality between r1p0 and r2p0
2. Functional Description
2.1. About the functions
2.1.1. Register renaming
2.1.2. Small loop mode
2.1.3. PTM interface
2.1.4. Performance monitoring
2.1.5. Virtualization of interrupts
2.2. Interfaces
2.2.1. Program Flow Trace and the Program Trace Macrocell interface
2.3. Clocking
2.3.1. Synchronous clocking
2.4. Dynamic high level clock gating
2.4.1. Gated blocks
2.4.2. Power Control Register
2.4.3. Effects of max_clk latency bits
2.4.4. Dynamic high level clock gating activity
2.5. Reset
2.5.1. Reset modes
2.5.2. Power-on reset
2.5.3. Processor reset
2.5.4. MPE SIMD logic reset
2.5.5. Debug reset
2.6. Power management
2.6.1. Energy efficiency features
2.6.2. Cortex-A9 processor power control
2.6.3. IEM Support
2.6.4. Cortex-A9 voltage domains
2.7. Constraints and limitations of use
3. Programmers Model
3.1. About the programmers model
3.2. The Jazelle extension
3.3. NEON technology
3.4. Memory formats
3.5. Addresses in the Cortex-A9 processor
3.6. Security extensions overview
3.6.1. System boot sequence
4. The System Control Coprocessors
4.1. About the system control coprocessor
4.2. Summary of system control coprocessor registers
4.2.1. Deprecated registers
4.2.2. System control registers
4.2.3. c0 summary table
4.2.4. TLB Type Register
4.2.5. Multiprocessor Affinity Register
4.2.6. Cache Size Identification Register
4.2.7. Cache Level ID Register
4.2.8. Auxiliary ID Register
4.2.9. Cache Size Selection Register
4.2.10. c1 summary table
4.2.11. System Control Register
4.2.12. Auxiliary Control Register
4.2.13. Coprocessor Access Control Register
4.2.14. Secure Debug Enable Register
4.2.15. Non-secure Access Control Register
4.2.16. Virtualization Control Register
4.2.17. c2 summary table
4.2.18. c3 summary table
4.2.19. c4, c5, and c6 summary tables
4.2.20. c7 summary table
4.2.21. c8 summary table
4.2.22. c9 summary table
4.2.23. c10 summary table
4.2.24. TLB Lockdown Register
4.2.25. c11 system control registers summary table
4.2.26. c12 summary table
4.2.27. Virtualization Interrupt Register
4.2.28. c13 summary table
4.2.29. c15 summary table
4.2.30. Power Control Register
4.2.31. NEON busy Register
4.2.32. Configuration Base Address Register
4.2.33. c15, TLB lockdown operations
4.3. CP14 Jazelle registers
4.4. CP14 Jazelle register descriptions
4.4.1. Jazelle Identity and Miscellaneous Functions Register
4.4.2. Jazelle Operating System Control Register
4.4.3. Jazelle Main Configuration Register
4.4.4. Jazelle Parameters Register
4.4.5. Jazelle Configurable Opcode Translation Table Register
5. Memory Management Unit
5.1. About the MMU
5.1.1. Memory Management Unit
5.2. TLB Organization
5.2.1. Micro TLB
5.2.2. Main TLB
5.3. Memory Access Sequence
5.4. MMU interaction with the memory system
5.5. External aborts
5.5.1. External aborts on data read or write
5.5.2. Synchronous and asynchronous aborts
6. Level 1 Memory System
6.1. About the L1 memory system
6.1.1. Memory system
6.2. Security extensions support
6.3. About the L1 instruction side memory system
6.3.1. Enabling program flow prediction
6.3.2. Program flow prediction
6.4. About the L1 data side memory system
6.4.1. Internal exclusive monitor
6.4.2. External aborts handling
6.5. Data prefetching
6.5.1. The PLD instruction
6.5.2. Data prefetching and monitoring
6.6. Parity error support
6.6.1. GHB and BTAC data corruption
7. Level 2 Memory Interface
7.1. Cortex-A9 L2 interface
7.1.1. About the Cortex-A9 L2 interface
7.1.2. AXI transaction IDs
7.1.3. AXI USER bits
7.1.4. Exclusive L2 cache
7.2. Optimized accesses to the L2 memory interface
7.2.1. Prefetch hint to the L2 memory interface
7.2.2. Early BRESP
7.2.3. Write full line of zeros
7.2.4. Speculative coherent requests
7.3. STRT instructions
8. Preload Engine
8.1. About the Preload Engine
8.2. PLE control register descriptions
8.2.1. PLE ID Register
8.2.2. PLE Activity Status Register
8.2.3. PLE FIFO Status Register
8.2.4. Preload Engine User Accessibility Register
8.2.5. Preload Engine Parameters Control Register
8.3. PLE operations
8.3.1. Preload Engine FIFO flush operation
8.3.2. Preload Engine pause channel operation
8.3.3. Preload Engine resume channel operation
8.3.4. Preload Engine kill channel operation
8.3.5. PLE Program New Channel operation
9. Performance Monitoring Unit
9.1. About the Performance Monitoring Unit
9.2. Performance monitoring events
9.2.1. Cortex-A9 specific events
10. Debug
10.1. About the debug interface
10.1.1. Debugging modes
10.1.2. Breakpoints and watchpoints
10.1.3. Asynchronous aborts
10.1.4. Processor interfaces
10.1.5. Effects of resets on debug registers
10.2. About the Cortex-A9 debug interface
10.2.1. Debug register access
10.3. Debug register descriptions
10.3.1. Debug State Cache Control Register (DBGDSCCR)
10.3.2. Breakpoint Value Registers
10.3.3. Breakpoint Control Registers
10.3.4. Watchpoint Value Registers
10.3.5. Watchpoint Control Registers
10.4. Management registers
10.4.1. Processor ID Registers
10.4.2. Identification Registers
10.5. External debug interface
10.5.1. Authentication signals
10.5.2. Changing the authentication signals
10.5.3. Debug APB interface
10.5.4. External debug request interface
A. Signal Descriptions
A.1. Clock and clock control signals
A.2. Resets and reset control
A.3. Interrupts
A.4. Configuration signals
A.5. Standby and Wait For Event signals
A.6. Power management signals
A.7. AXI interfaces
A.7.1. AXI Master0 signals
A.7.2. AXI Master1 signals
A.8. Performance monitoring signals
A.9. Exception flags signal
A.10. Parity signal
A.11. MBIST interface
A.12. Scan test signal
A.13. External Debug interface
A.13.1. Authentication interface
A.13.2. APB interface signals
A.13.3. CTI signals
A.13.4. Miscellaneous debug interface signals
A.14. PTM interface signals
B. Instruction Cycle Timings
B.1. About instruction cycle timing
B.2. Data-processing instructions
B.3. Load and store instructions
B.4. Multiplication instructions
B.5. Branch instructions
B.6. Serializing instructions
B.6.1. Serializing instructions
C. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Cortex-A9 uniprocessor system.
2.1. Cortex-A9 processor top-level diagram
2.2. PTM interface signals
2.3. ACLKENM0 used with a 3:1 clock ratio
2.4. Voltage domains for Cortex-A9 r2p0 designs
4.1. TLBTR bit assignments
4.2. MPIDR bit assignments
4.3. CCSIDR bit assignments
4.4. CLIDR bit assignments
4.5. CSSELR bit assignments
4.6. SCTLR bit assignments
4.7. ACTLR bit assignments
4.8. CPACR bit assignments
4.9. SDER bit assignments
4.10. NSACR bit assignments
4.11. VCR bit assignments
4.12. TLB Lockdown Register bit assignments
4.13. VIR bit assignments
4.14. Power Control Register bit assignments
4.15. NEON busy register bit assignments
4.16. Configuration Base Address Register bit assignments
4.17. Lockdown TLB index bit assignments
4.18. TLB VA Register bit assignments
4.19. Memory space identifier format
4.20. TLB PA Register bit assignments
4.21. Main TLB Attributes Register bit assignments
4.22. JIDR bit assignment
4.23. JOSCR bit assignments
4.24. JMCR bit assignments
4.25. Jazelle Parameters Register bit assignments
4.26. Jazelle Configurable Opcode Translation Table Register bit assignments
6.1. Branch prediction and instruction cache
6.2. Parity support
8.1. PLEIDR bit assignments
8.2. PLEASR bit assignments
8.3. PLESFR bit assignments
8.4. PLEUAR bit assignments
8.5. PLEPCR bit assignments
8.6. Program new channel operation bit assignments
10.1. Debug registers interface
10.2. Breakpoint Control Registers bit assignments
10.3. Watchpoint Control Registers bit assignments
10.4. External debug interface signals
10.5. Debug request restart-specific connections

List of Tables

1.1. Configurable options for the Cortex-A9 processor
2.1. Reset modes
2.2. Cortex-A9 processor power modes
3.1. Address types in the processor system
4.1. c0 system control registers
4.2. TLBTR bit assignments
4.3. MPIDR bit assignments
4.4. CCSIDR bit assignments
4.5. CLIDR bit assignments
4.6. CSSELR bit assignments
4.7. c1 system control registers
4.8. SCTLR bit assignments
4.9. ACTLR bit assignments
4.10. CPACR bit assignments
4.11. SDER bit assignments
4.12. NSACR bit assignments
4.13. VCR bit assignments
4.14. c2 system control registers
4.15. c3 system control register
4.16. c5 system control registers
4.17. c6 system control registers
4.18. c7 system control registers
4.19. c8 system control registers
4.20. c9 system control registers
4.21. c10 system control registers
4.22. TLB Lockdown Register bit assignments
4.23. c11 system control registers
4.24. c12 system control registers
4.25. Virtualization Interrupt Register bit assignments
4.26. c13 system control registers
4.27. c15 system control registers
4.28. Power Control Register bit assignments
4.29. Neon busy Register bit assignments
4.30. TLB lockdown operations
4.31. TLB VA Register bit assignments
4.32. TLB PA Register bit assignments
4.33. TLB Attributes Register bit assignments
4.34. CP14 Jazelle registers summary
4.35. JIDR bit assignments
4.36. JOSCR bit assignments
4.37. JMCR bit assignments
4.38. Jazelle Parameters Register bit assignments
4.39. Jazelle Configurable Opcode Translation Table Register bit assignments
7.1. AXI master 0 interface attributes
7.2. AXI master 1 interface attributes
7.3. ARUSERM0[6:0] encodings
7.4. ARUSERM1[6:0] encodings
7.5. ARUSERM0[8:0] encodings
7.6. Cortex-A9 mode and AxPROT values
8.1. PLEIDR bit assignments
8.2. PLEASR bit assignments
8.3. PLESFR bit assignments
8.4. PLEUAR bit assignments
8.5. PLEPCR bit assignments
8.6. PLE program new channel operation bit assignments
9.1. Performance monitoring instructions and Debug APB mapping
9.2. Cortex-A9 specific events
10.1. CP14 interface registers
10.2. BVRs and corresponding BCRs
10.3. Breakpoint Value Registers bit functions
10.4. Breakpoint Control Registers bit assignments
10.5. Meaning of BVR bits [22:20]
10.6. WVRs and corresponding WCRs
10.7. Watchpoint Value Registers bit functions
10.8. Watchpoint Control Registers bit assignments
10.9. Management registers
10.10. Processor Identifier Registers
10.11. Peripheral Identification Registers
10.12. Fields in the Peripheral Identification Registers
10.13. Peripheral ID Register 0 bit functions
10.14. Peripheral ID Register 1 bit functions
10.15. Peripheral ID Register 2 bit functions
10.16. Peripheral ID Register 3 bit functions
10.17. Peripheral ID Register 4 bit functions
10.18. Component Identification Registers
10.19. Authentication signal restrictions
10.20. PMU register names and Debug APB interface addresses
A.1. Clock and clock control signals for Cortex-A9
A.2. Cortex-A9 processor reset signals
A.3. Interrupt line signals
A.4. Configuration signals
A.5. CP15SDISABLE signal
A.6. Standby and wait for event signals
A.7. Power management signals
A.8. AXI-AW signals for AXI Master0
A.9. AXI-W signals for AXI Master0
A.10. AXI-B signals for AXI Master0
A.11. AXI-AR signals for AXI Master0
A.12. AXI-R signals for AXI Master0
A.13. AXI Master0 clock enable signal
A.14. AXI-AR signals for AXI Master1
A.15. AXI-R signals for AXI Master1
A.16. AXI Master1 clock enable signal
A.17. Performance monitoring signals
A.18. Event signals and event numbers
A.19. DEFLAGS signal
A.20. Parity signal
A.21. MBIST interface signals
A.22. MBIST signals with parity support implemented
A.23. MBIST signals without parity support implemented
A.24. Scan test signal
A.25. Authentication interface signals
A.26. APB interface signals
A.27. CTI signals
A.28. Miscellaneous debug signals
A.29. PTM interface signals
B.1. Data-processing instructions cycle timings
B.2. Single load and store operation cycle timings
B.3. Load multiple operations cycle timings
B.4. Store multiple operations cycle timings
B.5. Multiplication instruction cycle timings
C.1. Issue A
C.2. Differences between issue A and issue B
C.3. Differences between issue B and issue C
C.4. Differences between issue C and issue D
C.5. Differences between issue D and issue E

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Product Status

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Revision History
Revision A31 March 2008First release for r0p0
Revision B08 July 2008First release for r0p1
Revision C17 December 2008First release for r1p0
Revision D30 September 2009First release for r2p0
Revision E27 November 2009Second release for r2p0
Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0388E