Using this manual

This book is organized into the following chapters:

Chapter 1 Introduction

Read this for an introduction to the Cortex-A9 processor and descriptions of the major functional blocks.

Chapter 2 Functional Description

Read this for a description of the functionality of the Cortex-A9.

Chapter 3 Programmers Model

Read this for a description of the Cortex-A9 registers and programming details.

Chapter 4 The System Control Coprocessors

Read this for a description of the Cortex-A9 system registers and programming details.

Chapter 5 Memory Management Unit

Read this for a description of the Cortex-A9 Memory Management Unit (MMU) and the address translation process.

Chapter 6 Level 1 Memory System

Read this for a description of the Cortex-A9 level one memory system, including caches, Translation Lookaside Buffers (TLB), and store buffer.

Chapter 7 Level 2 Memory Interface

Read this for a description of the Cortex-A9 level two memory interface, the AXI interface attributes, and information about STRT instructions.

Chapter 8 Preload Engine

Read this for a description of the Preload Engine (PLE) and PLE operations.

Chapter 9 Performance Monitoring Unit

Read this for a description of the Cortex-A9 Performance Monitoring Unit (PMU) and associated events.

Chapter 10 Debug

Read this for a description of the Cortex-A9 support for debug.

Appendix A Signal Descriptions

Read this for a summary of the Cortex-A9 signals.

Appendix B Instruction Cycle Timings

Read this for a description of the Cortex-A9 instruction cycle timing.

Appendix C Revisions

Read this for a description of technical changes between released issues of this book.

Glossary

Read this for definitions of terms used in this book.

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