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The following sections describe the AXI Master1 interface signals, which are used for instruction accesses:
Table A.14 shows the AXI read address signals for AXI Master1.
Table A.14. AXI-AR signals for AXI Master1
| Name | I/O | Destination | Description |
|---|---|---|---|
| ARADDRM1[31:0] | O | AXI system devices | Address. |
| ARBURSTM1[1:0] | O | Burst type: b01 = INCR incrementing burst b10 = WRAP Wrapping burst. | |
| ARCACHEM1[3:0] | O | Cache type giving additional information about cacheable characteristics. | |
| ARIDM1[5:0] | O | Request ID. | |
| ARLENM1[3:0] | O | The number of data transfers that can occur within each burst. | |
| ARLOCKM1[1:0] | O | Lock type: b00 = Normal access. | |
| ARPROTM1[2:0] | O | Protection Type. | |
| ARREADYM1 | I | Address ready. | |
| ARSIZEM1[1:0] | O | AXI system devices | Burst size: b000 = 8-bit transfer b001 = 16-bit transfer b010 = 32-bit transfer b011 = 64-bit transfer. |
| ARUSERM1[4:0] | O | [4:1] = Inner attributes b0000 = Strongly-ordered b0001 = Device b0011 = Normal Memory Non-Cacheable b0110 = Write-Through b0111 = Write-Back no Write-Allocate b1111 = Write-Back Write-Allocate. [0] = Shared. | |
| ARVALIDM1 | O | Address valid. |
Table A.15 shows the AXI read data signals for AXI Master1.
Table A.15. AXI-R signals for AXI Master1
| Name | I/O | Source or destination | Description |
|---|---|---|---|
| RVALIDM1 | I | AXI system devices | Read valid |
| RDATAM1[63:0] | I | Read data | |
| RRESPM1[1:0] | I | Read response | |
| RLASTM1 | I | Read Last indication | |
| RIDM1[5:0] | I | Read ID | |
| RREADYM1 | O | Read ready |
This section describes the AXI Master1 clock enable signals. Table A.16 shows the AXI Master1 clock enable signals.
Table A.16. AXI Master1 clock enable signal
| Name | I/O | Source | Description |
|---|---|---|---|
| ACLKENM1 | I | Clock controller | Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock. See Clocking and resets. |
| Copyright © 2008-2010 ARM. All rights reserved. | ARM DDI 0388F |
| Non-Confidential | ID050110 |
| PDF version | |
| Home > Signal Descriptions > AXI interfaces > AXI Master1 signals instruction accesses |