11.3. Performance monitoring events

The Cortex-A9 processor implements the architectural events described in the ARM Architecture Reference Manual, with the exception of:

0x08

Memory-reading instruction architecturally executed

0x0E

Procedure return, other than exception return, architecturally executed.

For events and the corresponding PMUEVENT signals, see Table A.18.

The PMU provides an additional set of Cortex-A9 specific events.

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