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In the Cortex-A9 implementation of the Jazelle Extension:
Jazelle state is supported.
The BXJ instruction enters Jazelle
state.
Table 5.1 shows the CP14 Jazelle registers. For all Jazelle register accesses, CRm and Op2 are zero. All Jazelle registers are 32 bits wide.
Table 5.1. CP14 Jazelle registers summary
| Op1 | CRn | Name | Type | Reset | Page |
|---|---|---|---|---|---|
| 7 | 0 | Jazelle ID Register (JIDR) | RW[a] |
| Jazelle ID Register |
| 7 | 1 | Jazelle OS Control Register (JOSCR) | RW | - | Jazelle Operating System Control Register |
| 7 | 2 | Jazelle Main Configuration Register (JMCR) | RW | - | Jazelle Main Configuration Register |
| 7 | 3 | Jazelle Parameters Register | RW | - | Jazelle Parameters Register |
| 7 | 4 | Jazelle Configurable Opcode Translation Table Register | WO | - | Jazelle Configurable Opcode Translation Table Register |
[a] See Write operation of the JIDR for the effect of a write operation. | |||||
See the ARM Architecture Reference Manual for details of the Jazelle Extension.
| Copyright © 2008-2010 ARM. All rights reserved. | ARM DDI 0388F |
| Non-Confidential | ID050110 |
| PDF version | |
| Home > Jazelle DBX registers > CP14 Jazelle register summary |