Cortex-A9 Technical Reference ManualRevision: r2p2
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4.3.35. CP15 c15 register summary

Table 4.33 shows the system control registers you can access when CRn is c15.

Table 4.33. c15 system control registers

Op1CRmOp2NameTypeResetDescription
0c00Power Control RegisterRW[a][b]Power Control Register
c10NEON busy RegisterRO0x00000000NEON busy Register
4c00Configuration Base AddressRO[c][d]Configuration Base Address Register
5c42Select Lockdown TLB Entry for read WO[e]-TLB lockdown operations
4Select Lockdown TLB Entry for writeWOe-
c52Main TLB VA registerRWe-
c62Main TLB PA registerRWe-
c72Main TLB Attribute registerRW-

[a] RW in Secure state. Read only in Non-secure state.

[b] Reset value depends on the MAXCLKLATENCY[2:0] value. SeeConfiguration signals.

[c] RW in Secure privileged mode and RO in Non-secure state and user secure state.

[d] In Cortex-A9 uniprocessor implementations the configuration base address is set to zero.

     In Cortex-A9 MPCore implementations the configuration base address is reset to PERIPHBASE[31:13] so that software can determine the location of the private memory region.

[e] No access in Non-secure state.


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