4.3.22. CP15 c9 register summary
Table 4.21 shows
the system control registers you can access when CRn is c9.
Table 4.21. c9 system control registers
| Op1 | CRm | Op2 | Name | Type | Reset | Description |
|---|
| 0 | c12 | 0 | PMCR | RW | 0x41093000 | Performance Monitor Control Register |
| 1 | PMCNTENSET | RW | 0x00000000 | Count Enable Set Register |
| 2 | PMCNTENCLR | RW | 0x00000000 | Count Enable Clear Register |
| 3 | PMOVSR | RW | - | Overflow Flag Status Register |
| 4 | PMSWINC | WO | - | Software Increment Register |
| 5 | PMSELR | RW | 0x00000000 | Event Counter Selection Register |
| c13 | 0 | PMCCNTR | RW | - | Cycle Count Register |
| 1 | PMXEVTYPER | RW | - | Event Selection Register |
| 2 | PMXEVCNTR | RW | - | Performance Monitor Count Registers |
| c14 | 0 | PMUSERENR | RW[] | 0x00000000 | User Enable Register |
| 1 | PMINTENSET | RW | 0x00000000 | Interrupt Enable Set Register |
| 2 | PMINTENCLR | RW | 0x00000000 | Interrupt Enable Clear Register |
See Chapter 11 Performance Monitoring Unit.
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