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Table A.27 shows the CTI signals.
Table A.27. CTI signals
| Name | I/O | Source or destination | Description |
|---|---|---|---|
| EDBGRQ | I | External debugger or CoreSight interconnect | External debug request: 0 = No external debug request 1 = External debug request. The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK. |
| DBGACK | O | Debug acknowledge signal. | |
| DBGCPUDONE | O | Indicates that all memory accesses issued by the Cortex-A9 processor result from operations performed by a debugger. Active HIGH. | |
| DBGRESTART | I | Causes the core to exit from Debug state. It must be held HIGH until DBGRESTARTED is deasserted. 0 = Not enabled 1 = Enabled. | |
| DBGRESTARTED | O | Used with DBGRESTART to move between Debug state and Normal state. 0 = Not enabled 1 = Enabled. |