Cortex-A9 Technical Reference Manual: A.1. Clock and clock control signals

A.1. Clock and clock control signals

The Cortex-A9 processor has a single externally generated global clock. Table A.1 shows the clock and clock control signal.

Table A.1. Clock and clock control signals for Cortex-A9

Name	I/O	Source	Description
CLK	I	Clock controller	Global clock. See Clocking and resets.
MAXCLKLATENCY[2:0]	I	Implementation-specific static value	Controls dynamic clock gating delays. This pin is sampled during reset of the processor. See Dynamic high level clock gating

Name

I/O

Source

Description

CLK

Clock controller

Global clock.

MAXCLKLATENCY[2:0]

Implementation-specific static value

Controls dynamic clock gating delays.

This pin is sampled during reset of the processor.

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