Cortex-A9 Technical Reference Manual: 10.6. Debug management registers

10.6. Debug management registers

The Debug management registers define the standardized set of registers that is implemented by all CoreSight components. This section describes these registers.

You can access these registers:

through the internal CP14 interface
through the APB using the relevant offset when PADDRDBG[12]=0

See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for additional information about these registers.

Table 10.9 shows the contents of the management registers for the Cortex-A9 debug unit.

Table 10.9. Debug management registers

Register number	Offset	Name	CRn	Op1	CRm	OP2	Type	Description
960	`0xF00`	DBGITCTRL	c7	0	c0	4	RAZ/WI	Integration Mode Control Register
961-999	`0xF04- 0xF9C`	-					RAZ	Reserved
1000	`0xFA0`	DBGCLAIMSET	c7	0	c8	6	RW	Claim Tag Set Register
1001	`0xFA4`	DBGCLAIMCLR	c7	0	c9	6	RW	Claim Tag Clear Register
1002- 1003	`0xFA8-0xFBC`	-					RAZ	Reserved
1004	`0xFB0`	DBGLAR	c7	0	c12	6	WO	Lock Access Register
	`0xFB4`	DBGLSTR	c7	0	c13	6	RO	Lock Status Register
	`0xFB8`	DBGAUTHSTATUS	c7	0	c14	6	RO	Authentication Status Register
1007- 1009	`0xFBC-0xFC4`	-					RAZ	Reserved
1010	`0xFC8`	DBGDEVID	c7	0	c1	7	RAZ/WI	Device ID Register
1011	`0xFCC`	DBGDEVTYPE	c7	0	c3	7	RO	Device Type Register
1012- 1023	`0xFD0-0xFEC`	DBGPID	c7	0	c4-c8	7	RO	See Peripheral Identification Registers.
1020- 1023	`0xFF0-0xFFC`	DBGCID	c7	0	c12-c15	7	RO	See Component Identification Registers

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