Cortex-A9 Technical Reference Manual: 5.3.3. Jazelle Main Configuration Register

5.3.3. Jazelle Main Configuration Register

The JMCR characteristics are:

Purpose: Describes the Jazelle hardware configuration and its behavior.
Usage constraints: Only accessible in privileged modes.
Configurations: Available in all configurations.
Attributes: See the register summary in Table 5.1.

Figure 5.3 shows the JMCR bit assignments.

Figure 5.3. JMCR bit assignments

Table 5.4 shows the JMCR bit assignments.

Table 5.4. JMCR bit assignments

Bits	Name	Function
[31]	nAR	not Array Operations (nAR) bit. 0 = Execute array operations in hardware, if implemented. Otherwise, call the appropriate handlers in the VM Implementation Table. 1 = Execute all array operations by calling the appropriate handlers in the VM Implementation Table.
[30]	FP	The FP bit controls how the Jazelle hardware executes JVM floating-point opcodes: 0 = Execute all JVM floating-point opcodes by calling the appropriate handlers in the VM Implementation Table. 1 = Execute JVM floating-point opcodes by issuing `VFP` instructions, where possible. Otherwise, call the appropriate handlers in the VM Implementation Table. In this implementation FP is set to zero and is read-only.
[29]	AP	The Array Pointer (AP) bit controls how the Jazelle hardware treats array references on the operand stack: 0 = Array references are treated as handles. 1 = Array references are treated as pointers.
[28]	OP	The Object Pointer (OP) bit controls how the Jazelle hardware treats object references on the operand stack: 0 = Object references are treated as handles. 1 = Object references are treated as pointers.
[27]	IS	The Index Size (IS) bit specifies the size of the index associated with quick object field accesses: 0 = Quick object field indices are 8 bits. 1 = Quick object field indices are 16 bits.
[26]	SP	The Static Pointer (SP) bit controls how the Jazelle hardware treats static references: 0 = Static references are treated as handles. 1 = Static references are treated as pointers.
[25:1]	-	UNK/SBZP.
[0]	JE	The Jazelle Enable (JE) bit controls whether the Jazelle hardware is enabled, or is disabled: 0 = The Jazelle hardware is disabled: `BXJ` instructions behave like `BX` instructions setting the J bit in the CPSR generates a Jazelle-Disabled Jazelle exception. 1 = The Jazelle hardware is enabled: `BXJ` instructions enter Jazelle state setting the J bit in the CPSR enters Jazelle state.

To access the JMCR, read or write the CP14 register with:

MRC p14, 7, <Rd>, c2, c0, 0; Read JMCR
MCR p14, 7, <Rd>, c2, c0, 0; Write JMCR

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