| Copyright © 2008-2011 ARM. All rights reserved. | ARM DDI 0388G |
| Non-Confidential | ID072711 |
 PDF version | |
| Home > System Control > Register summary > Implementation defined registers |
| |||
| Home > System Control > Register summary > Implementation defined registers | |||
Table 4.27 shows the implementation defined registers. These registers provide test features and any required configuration options specific to the Cortex-A9 processor.
Table 4.27. Implementation defined registers
| CRn | Op1 | CRm | Op2 | Name | Type | Reset | Description |
|---|---|---|---|---|---|---|---|
| c1 | 0 | c0 | 1 | ACTLR[a] | RW | 0x00000000 | |
| 4 | c0 | 0 | Configuration Base Address | RO[b] | - [c] | Configuration Base Address Register | |
[a] RO in Non-secure state if NSACR[18]=0 and RW if NSACR[18]=1. [b] RW in secure privileged mode and RO in Non-secure state and User secure state. [c] In Cortex-A9 uniprocessor implementations the configuration base address is set to zero. In Cortex-A9 MPCore implementations the configuration base address is reset to PERIPHBASE[31:13] so that software can determine the location of the private memory region. | |||||||
| Copyright © 2008-2011 ARM. All rights reserved. | ARM DDI 0388G |
| Non-Confidential | ID072711 |
| PDF version | |
| Home > System Control > Register summary > Implementation defined registers |