| Copyright © 2008-2011 ARM. All rights reserved. | ARM DDI 0388G |
| Non-Confidential | ID072711 |
 PDF version | |
| Home > Level 1 Memory System > About the L1 memory system |
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The L1 memory system has:
separate instruction and data caches each with a fixed line length of 32 bytes
64-bit data paths throughout the memory system
support for four sizes of memory page
export of memory attributes for external memory systems
support for Security Extensions.
The data side of the L1 memory system has:
two 32-byte linefill buffers and one 32-byte eviction buffer
a 4-entry, 64-bit merging store buffer.
You must invalidate the instruction cache, the data cache, TLB, and BTAC before using them.
| Copyright © 2008-2011 ARM. All rights reserved. | ARM DDI 0388G |
| Non-Confidential | ID072711 |
| PDF version | |
| Home > Level 1 Memory System > About the L1 memory system |