Cortex-A9 Technical Reference ManualRevision: r4p0
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4.3.1. Main ID Register

The MIDR characteristics are:

Purpose

Provides identification information for the processor, including an implementer code for the device and a device ID number.

Usage constraints

The MIDR is:

  • a read-only register

  • common to the Secure and Non-secure states

  • only accessible in privileged modes.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.1 shows the MIDR bit assignments.

Figure 4.1. MIDR bit assignments

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Table 4.28 shows the MIDR bit assignments.

Table 4.28. MIDR bit assignments

BitsNameFunction
[31:24]Implementer

Indicates the implementer code:

0x41

ARM Limited.

[23:20]Variant

Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status, for example:

0x4

Major revision number.

[19:16]Architecture

Indicates the architecture code:

0xF

Defined by CPUID scheme.

[15:4]Primary part number

Indicates the primary part number:

0xC09

Cortex-A9.

[3:0]Revision

Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status, for example:

0x0

Minor revision number.


To access the MIDR, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c0, 0; Read Main ID Register
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