4.3.1. Main ID Register

The MIDR characteristics are:

Purpose

Provides identification information for the processor, including an implementer code for the device and a device ID number.

Usage constraints

The MIDR is:

  • a read-only register

  • common to the Secure and Non-secure states

  • only accessible in privileged modes.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.1 shows the MIDR bit assignments.

Figure 4.1. MIDR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.28 shows the MIDR bit assignments.

Table 4.28. MIDR bit assignments

BitsNameFunction
[31:24]Implementer

Indicates the implementer code:

0x41

ARM Limited.

[23:20]Variant

Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status, for example:

0x4

Major revision number.

[19:16]Architecture

Indicates the architecture code:

0xF

Defined by CPUID scheme.

[15:4]Primary part number

Indicates the primary part number:

0xC09

Cortex-A9.

[3:0]Revision

Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status, for example:

0x0

Minor revision number.


To access the MIDR, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c0, 0; Read Main ID Register
Copyright © 2008-2012 ARM. All rights reserved.ARM DDI 0388H
Non-ConfidentialID032812