Cortex-A9 Technical Reference Manual: A.7.1. AXI Master0 signals data accesses

The following sections describe the AXI Master0 interface signals used for data read and write accesses:

Table A.8 shows the AXI write address channel signals for AXI Master0.

Table A.8. Write address channel signals for AXI Master0

Name	I/O	Source or destination	Description
AWADDRM0[31:0]	O	AXI system devices	Address.
AWBURSTM0[1:0]	O		Burst type = b01, INCR incrementing burst.
AWCACHEM0[3:0]	O		Cache type giving additional information about cacheable characteristics, determined by the memory type and Outer cache policy for the memory region.
AWIDM0[1:0]	O		Request ID.
AWLENM0[3:0]	O	AXI system devices	The number of data transfers that can occur within each burst.
AWLOCKM0[1:0]	O		Lock type.
AWPROTM0[2:0]	O		Protection type.
AWREADYM0	I		Address ready.
AWSIZEM0[1:0]	O		Data transfer size: `b000` 8-bit transfer. `b001` 16-bit transfer. `b010` 32-bit transfe.r `b011` 64-bit transfer.
AWUSERM0[8:0]	O		[8] early BRESP. Used with L2C-310. [7] write full line of zeros. Used with the L2C-310. [6] clean eviction. [5] level 1 eviction. [4:1] memory type and Inner cache policy: `b0000` Strongly-ordered. `b0001` Device. `b0011` Normal Memory Non-Cacheable. `b0110` Write-Through. `b0111` Write-Back no Write-Allocate. `b1111` Write-Back Write-Allocate. [0] shared.
AWVALIDM0	O		Address valid.

Table A.9 shows the AXI write data signals for AXI Master0.

Table A.9. AXI-W signals for AXI Master0

Name	I/O	Source or destination	Description
WDATAM0[63:0]	O	AXI system devices	Write data
WIDM0[1:0]	O		Write ID
WLASTM0	O		Write last indication
WREADYM0	I		Write ready
WSTRBM0[7:0]	O		Write byte lane strobe
WVALIDM0	O		Write valid

Table A.10 shows the AXI write response channel signals for AXI Master0.

Table A.10. Write response channel signals for AXI Master0

Name	I/O	Source or destination	Description
BIDM0[1:0]	I	AXI system devices	Response ID
BREADYM0	O		Response ready
BRESPM0[1:0]	I		Write response
BVALIDM0	I		Response valid

Table A.11 shows the AXI read address channel signals for AXI Master0.

Table A.11. Read address channel signals for AXI Master0

Name	I/O	Source or destination	Description
ARADDRM0[31:0]	O	AXI system devices	Address.
ARBURSTM0[1:0]	O		Burst type: `b001` INCR incrementing burst. `b010` WRAP Wrapping burst.
ARCACHEM0[3:0]	O		Cache type giving additional information about cacheable characteristics.
ARIDM0[1:0]	O		Request ID.
ARLENM0[3:0]	O		The number of data transfers that can occur within each burst.
ARLOCKM0[1:0]	O		Lock type.
ARPROTM0[2:0]	O		Protection type.
ARREADYM0	I		Address ready.
ARSIZEM0[1:0]	O	AXI system devices	Burst size: `b000` 8-bit transfer. `b001` 16-bit transfer. `b010` 32-bit transfe.r `b011` 64-bit transfer.
ARUSERM0[4:0]	O		[4:1] memory type and Inner cache policy: `b0000` Strongly Ordered. `b0001` Device. `b0011` Normal Memory Non-Cacheable. `b0110` Write-Through. `b0111` Write-Back no Write-Allocate. `b1111` Write-Back Write-Allocate. [0] shared.
ARVALIDM0	O		Address valid.

Table A.12 shows the AXI read data channel signals for AXI Master0.

Table A.12. Read data channel signals for AXI Master0

Name	I/O	Source or destination	Description
RVALIDM0	I	AXI system devices	Read valid
RDATAM0[63:0]	I		Read data
RRESPM0[1:0]	I		Read response
RLASTM0	I		Read last indication
RIDM0[1:0]	I		Read ID
RREADYM0	O		Read ready

This section describes the AXI Master0 clock enable signals. Table A.13 shows the AXI Master0 clock enable signal.

Table A.13. Clock enable signal for AXI Master0

Name	I/O	Source	Description
ACLKENM0	I	Clock controller	Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock. See Clocking and resets.

Name

I/O

Source

Description

ACLKENM0

Clock controller

Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock.

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