| Copyright © 2008-2012 ARM. All rights reserved. | ARM DDI 0388H |
| Non-Confidential | ID032812 |
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The Cortex-A9 processor can generate prefetch hint requests to the L2 memory controller. The prefetch hint requests are non-compliant AXI read requests generated by the Cortex-A9 processor that do not expect any data return.
You can generate prefetch hint requests to the L2 by:
Enabling the L2 Prefetch Hint feature, bit [1] in the ACTLR. When enabled, this feature enables the Cortex-A9 processor to automatically issue L2 prefetch hint requests when it detects regular fetch patterns on a coherent memory. This feature is only triggered in a Cortex-A9 MPCore processor, and not in a uniprocessor.
Programming PLE operations, when this feature is available in the Cortex-A9 processor. In this case, the PLE engine issues a series of L2 prefetch hint requests at the programmed addresses. See Chapter 9 Preload Engine.
L2 prefetch hint requests are identified by having their ARUSER[5] bit set.
No additional programming of the L2C-310 is required.
| Copyright © 2008-2012 ARM. All rights reserved. | ARM DDI 0388H |
| Non-Confidential | ID032812 |
| PDF version | |
| Home > Level 2 Memory Interface > Optimized accesses to the L2 memory interface > Prefetch hint to the L2 memory interface |