Cortex-A9 Technical Reference ManualRevision: r4p0
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4.3.19. Preload Engine User Accessibility Register

The PLEUAR characteristics are:

Purpose

Controls whether PLE operations are available in User mode.

Usage constraints

The PLEUAR is:

  • common to Secure and Non-secure states

  • accessible in User and privileged modes, regardless of any configuration bit.

Configurations

Only available in configurations where the Preload Engine is present, otherwise an Undefined Instruction exception is taken.

Attributes

See Table 4.12.

Figure 4.18 shows the PLEUAR bit assignments.

Figure 4.18. PLEUAR bit assignments

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Table 4.45 shows the PLEUAR bit assignments.

Table 4.45. PLEUAR bit assignments

BitsNameFunction
[31:1]-RAZ.
[0]U

User accessibility:

1

User modes can access PLE registers and execute PLE operations.


To access the PLEUAR, read or write the CP15 register with:

MCR p15, 0, <Rt>, c11, c1, 0; Read PLEAUR
MRC p15, 0, <Rt>, c11, c1, 0; Write PLEAUR
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