Cortex-A9 Technical Reference ManualRevision: r4p0
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4.3.17. PLE Activity Status Register

The PLEASR characteristics are:

Purpose

Indicates whether the PLE engine is active.

Usage constraints

The PLEASR is:

  • common to Secure and Non-secure states

  • accessible in User and privileged modes, regardless of any configuration bit.

Configurations

Available in all Cortex-A9 configurations regardless of whether a PLE is present or not.

Attributes

See Table 4.12.

Figure 4.16 shows the PLEASR bit assignments.

Figure 4.16. PLEASR bit assignments

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Table 4.43 shows the PLEASR bit assignments.

Table 4.43. PLEASR bit assignments

BitsNameFunction
[31:1]-Reserved, RAZ
[0]R

PLE Channel running:

1

The Preload Engine is handling a PLE request.


To access the PLEASR, read the CP15 register with:

MRC p15, 0, <Rt>, c11, c0, 2; Read PLEASR
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