| Copyright © 2008-2012 ARM. All rights reserved. | ARM DDI 0388H |
| Non-Confidential | ID032812 |
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Table A.27 shows the CTI signals.
Table A.27. CTI signals
| Name | I/O | Source or destination | Description |
|---|---|---|---|
| EDBGRQ | I | External debugger or CoreSight interconnect | External debug request:
The processor treats the EDBGRQ input as level sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK. |
| DBGACK | O | Debug acknowledge signal. | |
| DBGCPUDONE | O | Indicates that all memory accesses issued by the Cortex-A9 processor result from operations that are performed by a debugger. active-HIGH. | |
| DBGRESTART | I | Causes the processor to exit from Debug state. It must be held HIGH until DBGRESTARTED is deasserted.
| |
| DBGRESTARTED | O | Used with DBGRESTART to move between Debug state and Normal state.
|
| Copyright © 2008-2012 ARM. All rights reserved. | ARM DDI 0388H |
| Non-Confidential | ID032812 |
| PDF version | |
| Home > Signal Descriptions > External Debug interface > CTI signals |