Cortex-A9 Technical Reference Manual: 7.3. About the L1 instruction side memory system

7.3. About the L1 instruction side memory system

The L1 instruction side memory system provides an instruction stream to the Cortex-A9 processor. To increase overall performance and to reduce power consumption, it contains the following functionality:

dynamic branch prediction
instruction caching.

Figure 7.1 shows this.

Figure 7.1. Branch prediction and instruction cache

The ISide comprises the following:

The Prefetch Unit (PFU)

The Prefetch Unit implements a 2-level prediction mechanism, comprising:

a 2-way BTAC, implemented in RAMs as:
2x256 entries
for the 512-entry BTAC.
2x512 entries
for the 1024-entry BTAC.
2x1024 entries
for the 2048-entry BTAC.
2x2048 entries
for the 4096-entry BTAC.
a Global History Buffer (GHB) containing 1024, 2048, 4096, 8192 or 16384 2-bit predictors implemented in RAMs
a return stack with eight 32-bit entries.
The prediction scheme is available in ARM state, Thumb state, ThumbEE state, and Jazelle state. It is also capable of predicting state changes from ARM to Thumb, and from Thumb to ARM. It does not predict
- any other state changes
- any instruction that changes the mode of the processor.
See Program flow prediction.

Instruction Cache Controller

The instruction cache controller fetches the instructions from memory depending on the program flow predicted by the prefetch unit.

The instruction cache is 4-way set associative. It comprises the following features:

configurable sizes of 16KB, 32KB, or 64KB
Virtually Indexed Physically Tagged (VIPT)
64-bit native accesses to provide up to four instructions per cycle to the prefetch unit
Security Extensions support
no lockdown support.

Copyright © 2008-2012 ARM. All rights reserved.	ARM DDI 0388H
Non-Confidential	ID032812
PDF version