Cortex-A9 Technical Reference ManualRevision: r4p0
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B.2. Data-processing instructions

Table B.1shows the execution unit cycle time for data-processing instructions.

Table B.1 shows the following cases:

no shift on source registers

For example, ADD r0, r1, r2

shift by immediate source register

For example, ADD r0, r1, r2 LSL #2

shift by register

For example, ADD r0, r1, r2 LSL r3.

Table B.1. Data-processing instructions cycle timings

InstructionNo shiftShift by
ConstantRegister

MOV

112

AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, CMN, ORR, BIC, MVN, TST, TEQ, CMP

123

QADD, QSUB,QADD8, QADD16, QSUB8, QSUB16, SHADD8, SHADD16, SHSUB8, SHSUB16,UQADD8, UQADD16, UQSUB8, UQSUB16,UHADD8, UHADD16, UHSUB8, UHSUB16,QASX, QSAX, SHASX, SHSAX,UQASX, UQSAX, UHASX, UHSAX

2--

QDADD, QDSUB, SSAT, USAT

3--

PKHBT, PKHTB

12-

SSAT16, USAT16, SADD8, SADD16, SSUB8, SSUB16,UADD8, UADD16, USUB8, USUB16, SASX, SSAX, UASX, USAX

1--

SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH

3--

SXTB, STXB16, SXTH, UXTB, UTXB16, UXTH

2--

BFC, BFI, UBFX, SBFX

2--

CLZ, MOVT, MOVW, RBIT, REV, REV16, REVSH, MRS

1--

MSR not modifying mode or control bits. See Serializing instructions.

1--

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