A.13.2. APB interface signals
Table A.26 shows
the APB interface signals.
Table A.26. APB interface signals
| Name | I/O | Source or
destination | Description |
|---|
| PADDRDBG[12:2] | I | CoreSight APB devices | Programming address. |
| PADDRDBG31 | I | APB address bus bit [31]: - 0
Not
an external debugger access. - 1
External debugger access.
|
| PENABLEDBG | I | Indicates a second and subsequent cycle of
a transfer. |
| PSELDBG | I | Debug registers select: - 0
Debug
registers not selected. - 1
Debug registers selected.
|
| PWDATADBG[31:0] | I | APB write data. |
| PWRITEDBG | I | APB read/write signal. |
| PRDATADBG[31:0] | O | APB read data bus. |
| PREADYDBG | O | APB slave ready. An APB slave can assert PREADY to extend a transfer. |
| PSLVERRDBG | O | APB slave error signal. |
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