PrimeCell® AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual 1.1.1. AHB interface

The interface converts the incoming AHB transfers to the protocol used internally by the AHB MC.

The interface has the following features:

all AHB fixed length burst types are directly translated to fixed length bursts
all undefined length INCR bursts are converted to INCR4 bursts
broken bursts are supported
the bufferable bit of the HPROT signal determines if the interface must wait for a write transfer to complete internally
a Read After Write (RAW) hazard detection buffer avoids RAW hazards
AHB response signals are registered to improve timing
locked transfers are supported within a 512MB region
HWDATA is registered to improve internal timing paths
a big-endian 32-bit mode option is implemented
AHB error response logic is removed as no internal components generate errors.

This interface is a fully validated component. This ensures that it obeys both the AHB protocol and the internal protocol that the interconnect uses.

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