PrimeCell® AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual 3.3.13. SMC Peripheral Identification Registers <0-3> at 0x1FE0-0x1FEC

3.3.13. SMC Peripheral Identification Registers <0-3> at 0x1FE0-0x1FEC

The smc_periph_id Registers are four 8-bit read-only registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single register that holds a 32-bit peripheral ID value. They are read by an external master to determine what version of the device the SMC is. None of the registers 0-3 can be read in the Reset state.

Table 3.14 lists the register bit assignments.

Table 3.14. smc_periph_id Register bit assignments

Bits	Name	Description
[31:25]	-	Reserved, read undefined.
[24]	integration_cfg	Configuration options are peripheral-specific. See SMC Peripheral Identification Register 3.
[23:20]	-	The peripheral revision number is revision-dependent.
[19:12]	designer	Designer’s ID number. This is `0x41` for ARM.
[11:0]	part_number	Identifies the peripheral. The part number for the SMC is `0x352`.

Figure 3.18 shows the correspondence between bits of the smc_ periph_id registers and the conceptual 32-bit Peripheral ID Register.

Figure 3.18. smc_periph_id Register bit assignments

The following section describe the smc_periph_id Registers

SMC Peripheral Identification Register 0

The smc_periph_id_0 Register is hard-coded and the fields within the register indicate the value. Table 3.15 lists the register bit assignments.

Table 3.15. smc_periph_id_0 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined
[7:0]	part_number_0	These bits read back as `0x52`

SMC Peripheral Identification Register 1

The smc_periph_id_1 Register is hard-coded and the fields within the register indicate the value. Table 3.16 lists the register bit assignments.

Table 3.16. smc_periph_id_1 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined
[7:4]	designer_0	These bits read back as `0x1`
[3:0]	part_number_1	These bits read back as `0x3`

SMC Peripheral Identification Register 2

The smc_periph_id_2 Register is hard-coded and the fields within the register indicate the value. Table 3.17 lists the register bit assignments.

Table 3.17. smc_periph_id_2 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined
[7:4]	revision	These bits read back as `0x3`
[3:0]	designer_1	These bits read back as `0x4`

SMC Peripheral Identification Register 3

The smc_periph_id_3 Register is hard-coded and the fields within the register indicate the value of 0x0. Table 3.18 lists the register bit assignments.

Table 3.18. smc_periph_id_3 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined.
[7:1]	-	Reserved for future use. Read undefined.
[0]	integration_cfg	When set, the integration test register map at address offset `0xE00` is present for reading and writing. If clear, the integration test registers have not been implemented.

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