PrimeCell ® AHB SRAM/NOR MemoryController (PL241) Technical Reference Manual

Revision:r0p1


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the AHB MC
1.1.1. AHB interface
1.1.2. AHB to APB bridge
1.1.3. SMC
1.1.4. Clock domains
1.1.5. Low-power interfaces
1.2. Supported devices
2. Functional Overview
2.1. Functional description
2.1.1. AHB interface
2.1.2. AHB to APB bridge
2.1.3. Clock domains
2.1.4. Low-power interface
2.2. SMC
2.2.1. SMC interface
2.2.2. APB slave interface
2.2.3. Format
2.2.4. Memory manager
2.2.5. Memory interface
2.2.6. Pad interface
2.2.7. Interrupts
2.3. Functional operation
2.3.1. AHB interface operation
2.3.2. AHB to APB bridge operation
2.3.3. Clock domain operation
2.3.4. Low-power interface operation
2.4. SMC functional operation
2.4.1. Operating states
2.4.2. Clocking and resets
2.4.3. Miscellaneous signals
2.4.4. APB slave interface operation
2.4.5. Format block
2.4.6. Memory manager operation
2.4.7. Interrupts operation
2.4.8. Memory interface operation
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Register descriptions
3.3.1. SMC Memory Controller Status Registerat 0x1000
3.3.2. SMC Memory Interface ConfigurationRegister at 0x1004
3.3.3. SMC Set Configuration Register at0x1008
3.3.4. SMC Clear Configuration Register at0x100C
3.3.5. SMC Direct Command Register at 0x1010
3.3.6. SMC Set Cycles Register at 0x1014
3.3.7. SMC Set Opmode Register at 0x1018
3.3.8. SMC Refresh Period 0 Register at 0x1020
3.3.9. SMC SRAM Cycles Registers <0-3> at 0x1100,0x1120, 0x1140, 0x1160
3.3.10. SMC Opmode Registers <0-3> at 0x1104,0x1124, 0x1144, 0x1164
3.3.11. SMC User Status Register at 0x1200
3.3.12. SMC User Configuration Register at0x1204
3.3.13. SMC Peripheral Identification Registers <0-3> at0x1FE0-0x1FEC
3.3.14. SMC PrimeCell Identification Registers <0-3> at0x1FF0-0x1FFC
4. Programmer’s Model for Test
4.1. SMC integration test registers
4.1.1. SMC Integration Configuration Registerat 0x1E00
4.1.2. Integration Inputs Register at 0x1E04
4.1.3. Integration Outputs Register at 0x1E08
5. Device Driver Requirements
5.1. Memory initialization
A. Signal Descriptions
A.1. About the signals list
A.2. Clocks and resets
A.3. AHB signals
A.4. SMC memory interface signals
A.5. SMC miscellaneous signals
A.6. Low-power interface
A.7. Configuration signal
A.8. Scan chains
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. AHB MC (PL241) configuration
2.1. AHB MC (PL241) configuration
2.2. AHB MC (PL241) clock domains
2.3. SMC block diagram
2.4. SMC SRAM pad interface external connections
2.5. Big-endian implementation
2.6. AHBC memory map
2.7. Request to enter low-power mode
2.8. AHB domain denying a low-power request
2.9. Accepting requests
2.10. SMC aclk domain FSM
2.11. Chip configuration registers
2.12. Device pin mechanism
2.13. Software mechanism
2.14. Asynchronous read
2.15. Asynchronous read in multiplexed-mode
2.16. Asynchronous write
2.17. Asynchronous write in multiplexed-mode
2.18. Page read
2.19. Synchronous burst read
2.20. Synchronous burst read in multiplexed-mode
2.21. Synchronous burst write
2.22. Synchronous burst write in multiplexed-mode
2.23. Synchronous read and asynchronouswrite
3.1. SMC register map
3.2. SMC configuration register map
3.3. SMC chip configuration register map
3.4. SMC user configuration register map
3.5. SMC peripheral and PrimeCell identification configurationregister map
3.6. smc_memc_status Register bit assignments
3.7. smc_memif_cfg Register bit assignments
3.8. smc_memc_cfg_set Register bit assignments
3.9. smc_memc_cfg_clr Register bit assignments
3.10. smc_direct_cmd Register bit assignments
3.11. smc_set_cycles Register bit assignments
3.12. smc_set_opmode Register bit assignments
3.13. smc_refresh_period_0 Register bitassignments
3.14. smc_sram_cycles Register bit assignments
3.15. smc_opmode Register bit assignments
3.16. smc_user_status Register bit assignments
3.17. smc_user_config Register bit assignments
3.18. smc_periph_id Register bit assignments
3.19. smc_pcell_id Register bit assignments
4.1. SMC integration test register map
4.2. smc_int_cfg Register bit assignments
4.3. smc_int_inputs Register bit assignments
4.4. smc_int_outputs Register bit assignments
5.1. SMC and memory initialization sheet1 of 3
5.2. SMC and memory initialization sheet 2 of 3
5.3. SMC and memory initialization sheet3 of 3
A.1. AHB MC PL241 grouping of signals

List of Tables

2.1. Static memory clocking options
2.2. Asynchronous read opmode chip register settings
2.3. Asynchronous read SRAM cycles register settings
2.4. Asynchronous read in multiplexed-mode opmode chip registersettings
2.5. Asynchronous read in multiplexed-mode SRAM cycles registersettings
2.6. Asynchronous write opmode chip register settings
2.7. Asynchronous write SRAM cycles register settings
2.8. Asynchronous write in multiplexed-mode opmode chip registersettings
2.9. Asynchronous write in multiplexed-mode SRAM cycles registersettings
2.10. Page read opmode chip register settings
2.11. Page read SRAM cycles register settings
2.12. Synchronous burst read opmode chip register settings
2.13. Synchronous burst read SRAM cycles register settings
2.14. Synchronous burst read in multiplexed-mode opmode chip register settings
2.15. Synchronous burst read in multiplexed-mode read SRAM cycles registersettings
2.16. Synchronous burst write opmode chip register settings
2.17. Synchronous burst write SRAM cycles register settings
2.18. Synchronous burst write in multiplexed-mode opmode chip register settings
2.19. Synchronous burst write in multiplexed-mode SRAM cycles register settings
2.20. Synchronous read and asynchronous write opmode chip register settings
2.21. Synchronous read and asynchronous write opmode chip register settings
3.1. Register summary
3.2. smc_memc_status Register bit assignments
3.3. smc_memif_cfg Register bit assignments
3.4. smc_memc_cfg_set Register bit assignments
3.5. smc_memc_cfg_clr Register bit assignments
3.6. smc_direct_cmd Register bit assignments
3.7. smc_set_cycles Register bit assignments
3.8. smc_set_opmode Register bit assignments
3.9. smc_refresh_period_0 Register bit assignments
3.10. smc_sram_cycles Register bit assignments
3.11. smc_opmode Register bit assignments
3.12. smc_user_status Register bit assignments
3.13. smc_user_config Register bit assignments
3.14. smc_periph_id Register bit assignments
3.15. smc_periph_id_0 Register bit assignments
3.16. smc_periph_id_1 Register bit assignments
3.17. smc_periph_id_2 Register bit assignments
3.18. smc_periph_id_3 Register bit assignments
3.19. smc_pcell_id Register bit assignments
3.20. smc_pcell_id_0 Register bit assignments
3.21. smc_pcell_id_1 Register bit assignments
3.22. smc_pcell_id_2 Register bit assignments
3.23. smc_pcell_id_3 Register bit assignments
4.1. SMC test register summary
4.2. smc_int_cfg Register bit assignments
4.3. smc_int_inputs Register bit assignments
4.4. smc_int_outputs Register bit assignments
A.1. Clocks and resets
A.2. AHB signals
A.3. SMC memory interface signals
A.4. SMC miscellaneous signals
A.5. Low-power interface signals
A.6. Configuration signal
A.7. Scan chain signals

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 17March 2006 First release for r0p0.
Revision B 20December 2006 Updated for r0p1.
Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Non-Confidential