A.2. Clocks and resets

Table A.1 lists the clocks and resets signals.

Table A.1. Clocks and resets

NameType

Source/

destination

Description
hclkInputClock sourceAHB clock
hresetnInputReset sourceAHB clock domain reset
dmc_aclkInputClock sourceDMC AHB clock
dmc_mclkInputClock sourceDMC memory clock
dmc_mclknInputClock sourceDMC inverted memory clock
dmc_mclkx2InputClock sourceDMC inverted memory clock
dmc_mclkx2nInputClock sourceDMC inverted memory clock
dmc_mresetnInputReset sourceDMC memory clock domain reset
smc_aclkInputClock sourceSMC AHB clock
smc_mclk0InputClock sourceSMC memory clock
smc_mclk0nInputClock sourceSMC inverted memory clock
smc_mreset0nInputReset sourceSMC memory clock domain reset
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