A.6. SMC memory interface signals

Table A.5 lists the SMC memory interface signals.

Table A.5. SMC memory interface signals

NameType

Source/

destination

Description
smc_data_in_0[15:0]InputMemoryData in
smc_busy_0InputMemoryBusy
smc_cs_n_0[1:0]OutputMemoryChip select
smc_ale_0OutputMemoryAddress latch enable
smc_cle_0OutputMemoryCommand latch enable
smc_we_n_0OutputMemoryWrite enable
smc_re_n_0OutputMemoryRead enable
smc_data_out_0[15:0]OutputMemoryData out
smc_data_en_0OutputMemoryData enable
smc_use_ebiInputMemoryUse EBI tie-off
smc_ebigrant0InputMemoryEBI grant
smc_ebibackoff0InputMemoryEBI back off
smc_ebireq0OutputMemoryEBI request
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