2.4.3. Bus matrix operation

The following sections explain the bus matrix configuration features and options:

Arbitration scheme

The bus matrix supports a round robin arbitration scheme. This enables each port to have an equal opportunity to access memory.

Locked transfers

A locked sequential transfer must be within the same 512MB address region to guarantee that it is to a single memory controller. To maintain data integrity throughout a locked sequence, the interconnect only accepts the locked transfer after the target slave has completed all outstanding transactions. The slave then becomes locked and only the locking master can access it. The slave remains locked until the locking master completes an unlocked transfer to that slave. This unlocking transfer is added by the AHB interface at the end of a locked sequence.

Memory map

The bus matrix is configured with predefined 512 MB regions of memory allocated to the internal memory controllers. Figure 2.12 shows the memory map.

Figure 2.12. Memory map

This enables the system designer maximum flexibility with memory regions for a fixed bus matrix memory map. You must program the address match and mask fields of the static and dynamic memory controllers to determine the address decode for each chip select. See DMC chip_<0-3>_cfg Registers at 0x0200 and SMC Opmode Registers <0-1> at 0x1104, 0x1124. The selected values must be within the constraints of the bus matrix memory map shown in Figure 2.12. The remap pin enables either the static or the dynamic memory controller to be decoded to address 0x00000000.

The SMC also contains some independent remap functionality. You can use the smc_remap_0 signal to alias SMC chip select 0 to address 0x00000000 in addition to its address match and mask tie-off. If the smc_remap_0 signal is HIGH, then the memory controller uses the smc_nand_mw_0 tie-off to determine the width of the external memory chip.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B
Non-Confidential