2.6.5. Format block

This section describes:

Hazard handling

There are four types of hazard:

  • Read After Read (RAR)

  • Write After Write (WAW)

  • Read After Write (RAW)

  • Write After Read (WAR).

The AHB interface deals with RAW hazards. WAR hazards do not occur in the AHB.

The SMC ensures the ordering of read transfers from a single port is maintained, RAR, and additionally that the ordering of write transfers from a single master is maintained, WAW.

NAND memory accesses

This section describes:

Two phase NAND access

The SMC defines two phases of commands when transferring data to/from NAND flash.

Command phase

Commands and optional address information are written to the NAND flash. The command and address can be associated with either a data phase operation to write to or read from the array, or a status/ID register transfer.

Data phase

Data is either written to or read from the NAND flash. This data can be either data transferred to or from the array, or status/ID register information.

The SMC uses information contained in the AHB address bus haddr[31:0] signals to determine whether the AHB transfer is a command or data phase access.

This information contained in the address bus additionally determines:

  • the value of the command

  • the number of address cycles

  • the chip select to be accessed.

During a command phase transfer, the address to be written to the NAND memory is transferred to the SMC using hwdata.

Table 2.6 lists the fields of the haddr[31:0] signal used to control a NAND flash transfer.

Table 2.6. NAND AHB address setup

AHB addressCommand phaseData phase
[31:24]Chip AddressChip Address
[23]NoOfAddCycles_2Reserved
[22]NoOfAddCycles_1Reserved
[21]NoOfAddCycles_0Clear CS
[20]End command validEnd command valid
[19]01
[18:11]End commandEnd command
[10:3]Start commandReserved
[2:0]ReservedReserved
NAND command phase transfers

A command phase transfer is always performed as an AHB write. The following information is contained in the AHB haddr[31:0] bus, and listed in Table 2.6:

Address cycles

The number of address cycles can be any value from zero to seven. Generally, up to five cycles are used during an array read or write, but a maximum of seven enables support for future devices.

Start command

The NAND command is used to initiate the required operation, for example:

  • a page read

  • page program

  • random page read

  • status or ID register read.

End command

The value of the second command, if required. This command is executed when all address cycles have completed. For example, some NAND memories require an additional command, following the address cycles, for a page read.

End command valid

Indicates whether the end command must be issued to the NAND flash.

Each address cycle consumes eight bits of address information. This is transferred to the SMC through the AHB write data.

Note

To ease system integration, the SMC supports the use of multiple AHB write transactions to transfer address information. The following restrictions apply in this case:

  • All other address information must be the same.

  • Data must be transferred in incrementing, consecutive accesses, that is, not wrapping.

NAND data phase transfers

Transfers data to/from the NAND flash, and can be performed as either an AHB read or write, depending on the required operation. The following information is contained in the haddr[31:0] bus, and shown in Table 2.6:

End command

The value of a command that is issued following the data transfer. This is required by some memories to indicate a page program following input of write data.

End command valid

Indicates whether the end command must be issued to NAND flash.

Clear CS

When set, the chip select for a NAND flash is de-asserted on completion of this command. When not set, the chip select remains asserted.

A NAND flash data phase program or read operation is expected to require multiple AHB transfers because of the large page size of NAND memories. You can therefore use the ClearCS bit to hold a chip select asserted while multiple AHB transfers transfer data to or from the NAND flash internal page. On the last AHB transfer, you can de-assert the chip select by setting the ClearCS bit.

Figure 2.30 and Figure 2.31 show the steps taken to perform NAND flash page read and page program operations respectively.

Figure 2.30. NAND flash page read operations

Figure 2.31. NAND flash page program operations

Note

You can poll for either a page program or page read completion in two ways:

  • Poll the raw_int_status0 bit in the smc_memc_status Register to determine when the memory smc_busy_0 input has gone HIGH, indicating a page program completion or read data ready.

  • In a system with multiple NAND flash devices connected to the SMC, the busy outputs are wire-ANDed to produce the single busy input to the SMC, that only transitions HIGH when all devices have completed. The status of each NAND chip can be determined by reading the individual device status register.

Figure 2.32 shows the steps taken to perform a NAND flash status register read.

Figure 2.32. NAND flash status register read

The process boxes shown in Figure 2.32 are defined as:

Command phase write

haddr = (start_cmd = STATUS_READ_CMD,

                  end_cmd = 0x0

                  end_valid = 0x0

                  addr_cycles = 0x0)

Note

Ensure burst length is a single.

hwdata = (don’t care)

Data phase read

haddr = (end_cmd = 0x0

                 end_valid = 0x0

                  clear_cs = 0x0)

Note

Ensure burst length is 1, the transfer is a single, the transfer size is eight or sixteen, hsize=0x0 or 0x1

hrdata = NAND flash status output

Note

Certain NAND flash devices can support multiple status register reads without reissuing the STATUS_READ_CMD. In this case the flow described in Figure 2.32 can be modified to include multiple data phase transfers for each command phase transfer.

The chip select being accessed is determined by the upper byte of the address bus, haddr[31:24]. The base address of external memory devices are defined by the smc_address_match0_<0-1>[7:0] and smc_address_mask0_<0-1>[7:0] tie-off pins. You can read the values of these tie-off pins through the opmode registers.

Booting from NAND flash

Because the format of AHB commands used to access NAND flash through the SMC, additional external logic is required to enable a processor to boot from this memory type. This additional logic enables boot code to be executed in-place from the first block within the NAND flash.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B
Non-Confidential