2.4.5. Low-power interface operation

The memory controller has three low-power interfaces. These interfaces indicate whether the clock for a specific domain can be switched off to reduce power consumption. It is expected that these interfaces are controlled by a system clock controller. One interface controls each of the following domains:

Each domain uses a simple three signal interface to indicate whether the clocks are required. The signals consist of:

a request input


an acknowledge output


an active output



<domain> is ahb, dmc or smc.

The following diagrams explain the protocol for the interface:

Figure 2.13 shows a request to enter low-power mode.

Figure 2.13. Request to enter low-power mode

The memory controller receives a request to enter low-power mode, indicated by <domain>_csysreq being driven LOW by the system clock controller, as shown at T1. The memory controller then has the chance to perform any required operations to prepare for the clock to be switched off. The memory controller acknowledges the request by asserting <domain>_csysack LOW, as shown at T2. At this point the <domain>_cactive signal is used to indicate whether the request has been accepted or denied. If the request is accepted, <domain>_cactive is LOW, as Figure 2.13 shows. If the request is denied, <domain>_cactive is HIGH. If the request is accepted, then the clock to that domain can be switched off. The peripheral is brought out of low-power state by restarting the clock and driving <domain>_csysreq HIGH, as shown at T4. The memory controller completes the handshake by driving <domain>_csysack HIGH, as shown at T5. Figure 2.14 shows the AHB domain denying a low-power request.

Figure 2.14. AHB domain denying a low-power request

When ahb_csysack is asserted LOW, the ahb_cactive signal is HIGH, as shown at T3, indicating the AHB domain is busy and the clock cannot be switched off. The handshake must be completed.

The AHB domain accepts or denies requests based on whether it is busy performing any transfers. Figure 2.15 shows that dynamic and static memory controllers always accept requests after they have performed the required operations to prepare the external memory for the clock to be switched off.

Figure 2.15. Accepting requests

The low-power request dmc_csysreq is driven LOW at time T1. When the memory controller is happy for the clock to be switched off, the dmc_csysack signal is driven LOW to acknowledge the request, as shown at T2. dmc_cactive is driven LOW, so the system clock controller knows the request has been accepted. When acknowledged, the system clock controller can disable both the dmc_aclk and dmc_mclk signals because the external memory is now in self refresh mode.

The three domains have separate interfaces to enable one or more domains to be switched off. The simple usage model is to switch off all domains. In this usage each individual low-power interface protocol must be observed before all the clocks can be disabled.

Another option is to put either the static or dynamic memory controller into low-power mode individually. This saves power on the memory controller not being used, while enabling the other memory controller to still perform data accesses. For example, if the system calculated that it did not require any data from dynamic memory for some considerable time it can use the DMC low-power interface to put the external memory into self refresh mode and then turn off the dmc_aclk and dmc_mclk signals. The memory controller can still access the static memory. In this situation, any access to the dynamic memory can cause the entire memory controller to stall as it waits for a response from the DMC that has no clock. You must take care to ensure that this scenario never arises.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B