2.5.7. Memory interface operation

The interface is separated from the arbiter using three configurable synchronous or asynchronous FIFOs:

There is also a static interface that has configuration signals that cannot be changed when the interface is operating.

The memory interface reads commands from the arbiter using a FIFO but only when that command can be executed. The memory interface ensures a command is only executed when all the inter-command delays, defined in this section, for that bank or chip are met. The memory interface enables multiple banks to be active at any one time. However, only one bank can be carrying out a data transfer at any one time. If the command at the head of the FIFO cannot be executed, then the command pipeline stalls until it can be executed.

You can program all the timing parameters in Figure 2.17 to Figure 2.27 using the APB interface. See Chapter 3 Programmer’s Model.

When the auto_power_down Register bit is set then the dmc_cke output pin is negated to take the external memories into active or precharge power down depending on whether there is a row open. See Figure 2.24. When exiting power down mode, the delay before the next command is issued is defined by the register value tXP.

There is an FSM to control the operation of the power-down mode. This FSM has a state that is entered when the SDRAM is put into Self-refresh mode. This is used so that if power is removed from all of the DMC apart from the memory interface and pad interface the state of the memory is known. When the rest of the DMC is powered-up the status FSM enters the Low-power state rather than the Config state.

Memory interface to pad interface timing

All command control outputs are clocked on the same edge. In Figure 2.16 to Figure 2.27 the control outputs to the external memory are always clocked on the falling edge of the memory clock.

The relative times between control signals from the memory interface are maintained when output from the pad interface to the actual SDRAM devices. Therefore, the timing register values required for a particular SDRAM device can be determined from the data sheet of the SDRAM device. Figure 2.16 to Figure 2.27 show how the data sheet timings map onto the DMC timing registers.

The times in Figure 2.16 to Figure 2.27 are not necessarily the default timing values but are values that are small enough to show the entire delay in one figure.

Note

The command_en, data_cntl_en, and read_en signals are internal to the DMC.

Figure 2.16 shows the command control output timing.

Figure 2.16. Command control output timing

Figure 2.17 shows the activate to read or write command timing.

Figure 2.17. Activate to read or write command timing, tRCD

Figure 2.18 shows the bank activate to bank activate or auto-refresh command timing.

Figure 2.18. Bank activate to bank activate or auto-refresh command timing, tRC

Figure 2.19 shows the bank activate to different bank activate for a memory timing.

Figure 2.19. Bank activate to different bank activate for a memory timing, tRRD

Figure 2.20 shows the precharge to command and auto-refresh timing.

Figure 2.20. Precharge to command and auto-refresh timing, tRP and tRFC

Figure 2.21 shows activate to precharge, and precharge to precharge timing.

Figure 2.21. Activate to precharge, and precharge to precharge timing, tRAS and tRP

Figure 2.22 shows mode register write to command timing.

Figure 2.22. Mode register write to command timing, tMRD

Figure 2.23 shows self-refresh entry and exit timing.

Figure 2.23. Self-refresh entry and exit timing, tESR and tXSR

Figure 2.24 shows power-down entry and exit timing.

Figure 2.24. Power down entry and exit timing, tXP

The pwr_down_prd count is timed from the memory interface becoming idle, that is after a command delay has timed out or the read data FIFO is emptied. dmc_cke is asserted when the command FIFO is not empty.

Figure 2.25 shows the turnaround time, tWTR, for the memory interface to output a Write command followed immediately by a Read command.

Figure 2.25. Data output timing, tWTR

Figure 2.26 shows the relationship between memory interface outputting the Write command and the WDATA when tDQSS is set to 1. It also highlights the tWR minimum time between a Write and a Precharge command.

Figure 2.26. Data output timing, tDQSS = 1

Figure 2.27 shows the timing relationship between the Read command being output from the memory interface and the RDATA being returned to the memory interface from the pad interface.

Figure 2.27. Data input timing

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