2.5.4. Arbiter operation

This section describes:

Formatting from the DMC interface

Formatting is as follows:

Chip select decoding

Using the programmed values in the dmc_chip_<0-3>_cfg Registers defined in Chapter 3 Programmer’s Model, an incoming address has the most significant eight address bits when compared with the address match bits. The later method uses the address mask to ignore any don't care bits to select an external chip.

The transfer is still carried out if there is no match but the result is undefined.

Row select decoding

The row address is determined from the address using bits [5:3] of the dmc_memory_cfg Register, and also the brc_n_rbc bit for the selected chip defined in the dmc_chip_<0-3>_cfg Register.

Column select decoding

The column address is determined from the address using bits [2:0] of the dmc_memory_cfg Register.

Bank select decoding

The chip bank is determined using the brc_n_rbc bit for the selected chip defined in the dmc_chip_<0-3>_cfg Register.

Number of beats

The number of memory beats is determined, depending on the effective external memory width and the burst size of the access. Wrapping bursts are split into two incrementing bursts.

Quality of Service (QoS) selection

QoS is defined for the DMC as a method of increasing the arbitration priority of a read access that requires low-latency read data. The QoS for a read access is determined when it is received by the arbiter. There is no quality of service for write accesses.

There are two forms of quality of service tracking:

  • qos_max time-out

  • qos_min time-out.

Example 2.1 shows that the type of QoS and QoS value is determined by the dmc_id_<0-5>_cfg Register.

Example 2.1. 

If a transfer is received from port 1, the dmc_id_1_cfg Register determines the qos_enable, qos_min, and qos_max values for this transfer. If the qos_enable bit is HIGH then the new arbiter entry that is created for this transfer is assigned the qos_min value and qos_max value from the dmc_id_1_cfg Register. In addition to this, if the qos_override bit associated with this port, dmc_qos_override[1], is HIGH when the transfer is accepted then the qos_min arbiter entry is forced HIGH irrespective of whether the qos_enable bit is HIGH.

See DMC id_<0-5>_cfg Registers at 0x0100.

Formatting from the memory manager

The direct command bits [21:20] determines the memory chip to access.

The command to be carried out is either an auto refresh, or from the APB interface. The memory manager encodes it to match the format required by the arbiter.

Arbiter access mux

The selection of a command from the DMC interface or the memory manager is fixed, with the memory manager having a higher priority.

The selection between a DMC read access and a write access is made using a round-robin arbitration, unless a read access has a low latency QoS value. In this case it is arbitrated immediately.

QoS

For write accesses, no quality of service is provided.

If the QoS enable bit for the port is set in the register bank, the QoS maximum latency value is decremented every cycle until it reaches zero.

If the entry is still in the queue when the QoS maximum latency value reaches zero then the entry becomes high priority. This is called a time-out. Also, any entry in the queue with a minimum latency QoS also produces a time-out. Minimum latency time-outs have priority over maximum latency time-outs.

A QoS is also provided for the auto-refresh commands from the memory manager. The arbiter keeps track of the number of auto-refresh commands in the arbiter queue with a simple increment-decrement counter. If the number of auto-refresh commands reaches a set limit of six, a refresh time-out is signalled to the arbiter queue. This forces all of the auto-refresh queue entries to have a time-out. This time-out is sticky, and does not disappear when the number of time-outs drops back below the threshold. Instead, it remains asserted until all of the auto-refreshes have been serviced. This provides a guaranteed refresh rate in the SDRAM.

Hazard detection

There are two types of hazard:

Read After Read (RAR)

There is a read already in the arbiter queue with the same ID as the incoming entry, and it is also a read.

Write After Write (WAW)

There is a write already in the arbiter queue with the same ID as the incoming entry, and it is also a write.

The arbiter entry is flagged as having a dependency if a hazard is detected. There might be dependencies against a number of other arbiter entries. As the arbiter entries are invalidated, so the dependencies are reduced until finally there are no outstanding dependencies and the entry is free to start.

Note

There are no Read-After-Write (RAW) or Write-After-Read (WAR) hazard checks in the DMC.

Scheduler

The scheduler keeps track of the activity of the bank, FSMs in the memory interface. This enables the arbiter to select an entry from the queue that does not stall the memory pipeline.

Arbitration algorithm

This is combinatorial logic that selects the read pointer from the current queue state.

The ordering of commands to be carried out from the arbiter queue is arbitrated with a priority scheme of the following order:

  1. read min-latency timeout

  2. read max-latency timeout.

If the last command was an open-row access:

  • next access to a bank, for which there are no pending open-row accesses, that is an open-row miss.

If the last open-row access was a read:

  1. open-row read

  2. open-row write.

Else:

  1. open-row write

  2. open-row read

  3. open-row miss.

Command formatting

For every memory burst access necessary to complete an arbiter queue entry, a memory interface command is required.

Command formatting calculates the number of memory interface commands and memory cycles for each command to complete the next arbiter queue entry that is to be sent to the memory interface. It contains an address incrementor and a beat decrementor so that the arbiter entry can be interrupted and restarted.

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