2.1.4. Clock domains

The memory controller has the following clock domains:

AHB clock domain

This is clocked by hclk, dmc_alk, and smc_aclk and is reset by hresetn.

Dynamic memory clock domain

This is clocked by dmc_mclk, dmc_mclkn, dmc_mclkx2, dmc_mclkx2n and reset by dmc_mresetn.

Static memory clock domain

This is clocked by smc_mclk0, and smc_mclk0n and is reset by smc_mreset0n.

Figure 2.2 shows the clock domains.

Figure 2.2. AHB MC (PL244) clock domains

The memory controller supports many different options for clocking the different domains. The DMC and SMC clock domains are completely independent and each have clocking options.

See Clock domain operation for more information.

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