2.6.7. Interrupts operation

The busy outputs of each NAND chip are wire-ANDed together outside the SMC to create a single interrupt input. Multiple outstanding accesses to NAND chips only trigger an interrupt when all chips have completed the respective operations. During the busy phase you can read the status register of each chip to determine the chips that have completed.

An interrupt is cleared by the next AHB read to any chip select on the memory interface.

The interrupt outputs are generated through a combinational path from the relevant input pin. This enables the SMC to be placed in Low-power state, and the clocks stopped, while waiting for an interrupt.

When interrupts are disabled, a synchronized version of the interrupt input is still readable through the APB interface. This enables software to poll, rather than use an interrupt to determine when NAND operations can proceed.

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