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The memory interface issues commands to the memory from the command FIFO, and controls the cycle timings of these commands. A new command is only issued when the previous command is complete and any turn-around times have been met. Additionally, a read command is not issued unless there is space for all the impending data in the read data FIFO.
If enabled, the EBI can prevent commands being issued when the SMC is not granted the external bus.
The NAND timing parameters are shown in Figure 2.34 to Figure 2.35.
The internal signal read_data is included in the read transfer waveforms to indicate the clock edge on which data is registered by the SMC.
All NAND control and data outputs are registered on the falling edge of smc_mclk0. Additionally read data from the memory device is registered by the SMC on the falling edge of smc_mclk0 before being pushed onto the read data FIFO.
NAND opmode registers only set memory width and are not included in this section.
This subsection describes:
Command phase access
Data phase access
NAND read example
NAND write example.
Table 2.7 lists the smc_opmode0_<0-1> and NAND Register settings.
Table 2.7. NAND cycles register settings for command
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_ar | t_rr |
| Value | - | b011 | - | b010 | - | - | - | - |
Figure 2.34 shows an address input phase. The cycle time is set to three, and the smc_we_n_0 assertion duration set to two. The address consists of four cycles, and the second command is not required.
Table 2.8 lists example haddr fields for NAND flash address input.
Table 2.9 lists the smc_opmode0_<0-1> and NAND Register settings.
Table 2.9. NAND cycles register settings for read
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_ar | t_rr |
| Value | b011 | - | b010 | - | - | - | - | - |
Figure 2.35 shows a read from NAND flash. The cycle time is set to three and the smc_re_n_0 assertion delay to two cycles. Four data items are read.
Table 2.10 lists example haddr fields for NAND flash page read.
Table 2.10. NAND flash page read example haddr fields
| haddr bit field | Value | Description |
|---|---|---|
| [31:24] | chip select | - |
| [23:22] | b00 | Reserved |
| [21] | b1 | Last transfer, de-assert chip select when complete |
| [20] | b0 | End command not required |
| [19] | b1 | Data phase transfer |
| [18:11] | b0000_0000 | Reserved |
| [10:3] | b0000_0000 | Reserved |
| [2:0] | b000 | Address alignment |
Read data phases cannot have end commands associated with them.
Table 2.11 lists the smc_opmode0_<0-1> and NAND Register settings.
Table 2.11. NAND cycles register settings for write
| Field | t_rc | t_wc | t_rea | t_wp | t_clr | t_ar | t_ar | t_rr |
| Value | - | b011 | - | b010 | - | - | - | - |
Figure 2.36 shows a write to NAND flash. The cycle time is set to three and the smc_we_n_0 assertion duration to two cycles. Four data items are written.
Table 2.12 lists example haddr fields for NAND flash page write.
Table 2.12. NAND flash page write example haddr fields
| haddr bit field | Value | Description |
|---|---|---|
| [31:24] | chip select | - |
| [23:22] | b00 | Reserved |
| [21] | b1 | Last transfer, de-assert chip select when complete |
| [20] | b1 | End command required |
| [19] | b1 | Data phase transfer |
| [18:11] | b0000_0000 | CMD2 |
| [10:3] | b0000_0000 | Reserved |
| [2:0] | b000 | Address alignment |
Figure 2.37 shows a NAND read example, including the delay inserted by the memory device.
Figure 2.38 shows a NAND write example, including the delay inserted by the memory device.
| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0392B |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > SMC functional operation > Memory interface operation |