2.6.8. Memory interface operation

The memory interface issues commands to the memory from the command FIFO, and controls the cycle timings of these commands. A new command is only issued when the previous command is complete and any turn-around times have been met. Additionally, a read command is not issued unless there is space for all the impending data in the read data FIFO.

If enabled, the EBI can prevent commands being issued when the SMC is not granted the external bus.

The NAND timing parameters are shown in Figure 2.34 to Figure 2.35.

The internal signal read_data is included in the read transfer waveforms to indicate the clock edge on which data is registered by the SMC.

NAND timing tables and diagrams

All NAND control and data outputs are registered on the falling edge of smc_mclk0. Additionally read data from the memory device is registered by the SMC on the falling edge of smc_mclk0 before being pushed onto the read data FIFO.

Note

NAND opmode registers only set memory width and are not included in this section.

This subsection describes:

  • Command phase access

  • Data phase access

  • NAND read example

  • NAND write example.

Command phase access

Table 2.7 lists the smc_opmode0_<0-1> and NAND Register settings.

Table 2.7. NAND cycles register settings for command

Fieldt_rct_wct_reat_wpt_clrt_art_art_rr
Value-b011-b010----

Figure 2.34 shows an address input phase. The cycle time is set to three, and the smc_we_n_0 assertion duration set to two. The address consists of four cycles, and the second command is not required.

Figure 2.34. Nand flash command phase

Table 2.8 lists example haddr fields for NAND flash address input.

Table 2.8. NAND flash address input example haddr fields

haddr bit fieldValueDescription
[31:24]chip select-
[23:21]b1004 address cycles
[20]b0End command not required
[19] b0Command phase transfer
[18:11]CMD2-
[10:3]CMD1-
[2:0] b000Address alignment
Data phase access

Table 2.9 lists the smc_opmode0_<0-1> and NAND Register settings.

Table 2.9. NAND cycles register settings for read

Fieldt_rct_wct_reat_wpt_clrt_art_art_rr
Valueb011-b010-----

Figure 2.35 shows a read from NAND flash. The cycle time is set to three and the smc_re_n_0 assertion delay to two cycles. Four data items are read.

Figure 2.35. NAND flash read data phase

Table 2.10 lists example haddr fields for NAND flash page read.

Table 2.10. NAND flash page read example haddr fields

haddr bit fieldValueDescription
[31:24]chip select-
[23:22]b00Reserved
[21]b1Last transfer, de-assert chip select when complete
[20]b0End command not required
[19]b1Data phase transfer
[18:11]b0000_0000Reserved
[10:3]b0000_0000Reserved
[2:0]b000Address alignment

Note

Read data phases cannot have end commands associated with them.

Table 2.11 lists the smc_opmode0_<0-1> and NAND Register settings.

Table 2.11. NAND cycles register settings for write

Fieldt_rct_wct_reat_wpt_clrt_art_art_rr
Value-b011-b010----

Figure 2.36 shows a write to NAND flash. The cycle time is set to three and the smc_we_n_0 assertion duration to two cycles. Four data items are written.

Figure 2.36. NAND flash write data phase

Table 2.12 lists example haddr fields for NAND flash page write.

Table 2.12. NAND flash page write example haddr fields

haddr bit fieldValueDescription
[31:24]chip select-
[23:22]b00Reserved
[21]b1Last transfer, de-assert chip select when complete
[20]b1End command required
[19]b1Data phase transfer
[18:11]b0000_0000CMD2
[10:3]b0000_0000Reserved
[2:0]b000Address alignment
NAND Read example

Figure 2.37 shows a NAND read example, including the delay inserted by the memory device.

Figure 2.37. NAND read example

NAND write example

Figure 2.38 shows a NAND write example, including the delay inserted by the memory device.

Figure 2.38. NAND write example

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