2.5.10. Power-down support and usage model

The DMC provides architectural support for low-power operation in three ways:

Additionally, the DMC microarchitecture provides additional power savings through extensive use of clock gating. This includes clock gating of the external memory clocks by selecting the stop_mem_clock bit in the dmc_memory_cfg Register.

It is possible to implement DMC with two power domains:

See Figure 2.2.

Table 2.4 lists the valid system states of the dmc_aclk domain FSM and the dmc_mclk domain FSM. It also shows the valid power, clock, and reset states in the dmc_aclk and dmc_mclk domains. Figure 2.28 shows the valid transitions, and the text following it explains how to traverse the system states.

Table 2.4. Valid system states for FSMs

SDRAMDMCSystem state
  aclk FSMmclk FSM 
VDDStateVDDClockResetStateVDDClockResetState 
0Null0N/aN/aNull0N/aN/aNull1
0Null>0RunningNoPOR>0RunningNoPOR2
0Null>0RunningYesReset>0RunningYesReset3
0Null>0RunningNoConfig>0RunningNoPowered_ up4
>0Accessible>0RunningNoConfig>0RunningNoPowered_ up5
>0Accessible>0RunningNoReady>0RunningNoPowered_ up6
>0Powered- down>0RunningNoReady>0RunningNoPowered_ down7
>0Self_ refresh>0RunningNoLow_ power>0RunningNoSelf_ refresh8
>0Self_ refresh>0RunningNoLow_ power>0StoppedNoSelf_ refresh9
>0Self_ refresh>0StoppedNoLow_ power>0RunningNoSelf_ refresh10
>0Self_ refresh>0StoppedNoLow_ power>0StoppedNoSelf_ refresh11
>0Self_ refresh0N/aN/aNull>0StoppedNoSelf_ refresh12
>0Self_ refresh0N/aN/aNull>0RunningNoSelf_ refresh13
>0Self_ refresh>0RunningNoPOR>0StoppedNoSelf_ refresh14
>0Self_ refresh>0RunningNoPOR>0RunningNoSelf_ refresh15
>0Self_ refresh>0RunningYesReset>0StoppedNoSelf_ refresh16
>0Self_ refresh>0RunningYesReset>0RunningNoSelf_ refresh17

The ranking of system power states, from highest power to lowest power, is as follows: 6, 7, 8, 10, 9, 11, 13, 12.

However, states 8-11 are similar and the recommendation is to use state 11 from this group if clock-stopping techniques are available. Similarly, states 12 and 13 are similar and the recommendation is to use state 12 from this pair. Table 2.5 lists a recommended set of power states.

Table 2.5. Recommended power states

System statePower name
6Running
7Auto power-down
11Shallow self-refresh
12Deep self-refresh

These states and arcs are highlighted in Figure 2.28.

Note

Arcs are lines between states.

States 1-5, 9, 14, and 16 are only used as transitional states.

Figure 2.28. DMC system state transitions

State transitions are as follows:

Arc 1 to 2

Apply power to all DMC power domains, and ensure that dmc_aclk and dmc_mclk are running.

Arc 2 to 3

Assert reset in both the dmc_aclk reset domain and the dmc_mclk reset domain.

Arc 3 to 4

Deassert reset in both the dmc_aclk reset domain and the dmc_mclk reset domain.

Arc 4 to 5

Apply power to the SDRAM power domain.

Arc 5 to 6

You must:

  1. Write to all of the memory timing parameters, address offsets 0x0014 to 0x0044.

  2. Write to the dmc_memory_cfg and dmc_refresh_prd Registers, address offsets 0x000C and 0x0010.

  3. Initialize the memory, using the dmc_direct_cmd Register, offset 0x0008, with the sequence of commands specified by the memory vendor. When you have sent these commands to the memory, you can write to the dmc_memc_cmd Register, offset 0x0004 with the GO command, 0x0.

  4. Poll the dmc_memc_status Register until the value of 0x1 is returned, READY, signifying that the DMC is ready to accept accesses to the SDRAM.

Arc 6 to 5

If you want to reconfigure either the DMC or SDRAM, you must first write to the dmc_memc_cmd Register, offset 0x0004, with the Pause command, 0x3, and poll the dmc_memc_status Register until the value of 0x2 is returned, Paused. Then you can write to the dmc_memc_cmd Register with the Configure command, 0x4 and poll the dmc_memc_status Register until the value of 0x0000 is returned, Config.

Arc 6 to 7

If auto_power_down is set in the dmc_memory_cfg Register (see DMC Memory Configuration Register at 0x000C) then this arc is automatically taken when the SDRAM has been idle for power_down_prd multiplied by dmc_mclk cycles, for example, 10 x dmc_mclk cycles.

Arc 7 to 6

When an SDRAM access command has been received in the dmc_mclk domain, this arc is taken.

Arc 6 to 8

You can take this arc under either hardware or software control:

  • To take this arc under software control:

    1. Issue the Pause command.

    2. Poll for the Paused state.

    3. Issue the Sleep command.

  • To take this arc under hardware control, use the DMC low-power interface to request a Low-power state.

Arc 6 to 9

The same as arc 6 to 8, but additionally stop the mclk domain clock.

Arc 6 to 10

The same as arc 6 to 8, but additionally stop the dmc_aclk domain clock.

Arc 6 to 11

The same as arc 6 to 8, but additionally stop both the dmc_mclk and the dmc_aclk domain clocks.

Arc 6 to 12

The same as arc 6 to 8, but additionally stop the dmc_mclk domain clock and remove power from the dmc_aclk power domain. You can only do this if the DMC implementation has separate power domains for dmc_aclk and dmc_mclk.

Arc 6 to 13

The same as arc 6 to 8, but additionally remove power from the dmc_aclk power domain. You can only do this if the DMC implementation has separate power domains for dmc_aclk and dmc_mclk.

Arc 8 to 6

You can take this arc under either hardware or software control:

  • To take this arc under software control:

    1. Issue the Wakeup command to the memc_cmd Register.

    2. Poll the dmc_memc_status Register for the Paused state.

    3. Issue the Go command and poll for the Ready state.

  • To take this arc under hardware control, use the DMC low-power interface to bring the DMC out of a Low-power state.

Arc 9 to 6

The same as arc 8 to 6, but you must first start the dmc_mclk domain clock.

Arc 10 to 6

The same as arc 8 to 6, but you must first start the dmc_aclk domain clock.

Arc 11 to 6

The same as arc 8 to 6, but you must first start both the dmc_aclk and dmc_mclk domain clocks.

Arc 12 to 14

Apply power to the dmc_aclk power domain.

Arc 14 to 16

Assert reset to the dmc_aclk reset domain.

Arc 16 to 9

Deassert reset to the dmc_aclk reset domain.

Arc 13 to 15

Apply power to the dmc_aclk power domain.

Arc 15 to 17

Assert reset to the dmc_aclk reset domain.

Arc 17 to 8

Deassert reset to the dmc_aclk reset domain.

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