2.4.4. Clock domain operation

The memory controller supports three clock domains.

The hclk input drives the AHB clock domain. This clock drives the AHB interfaces and bus matrix. Each of the internal memory controllers has a separate clock input in this domain. These are called dmc_aclk and smc_aclk. These signals are separated to enable the clock to be stopped on an individual memory controller for low-power operation, see Low-power interface operation. These three clocks must always be driven from the same clock source. The input signal hresetn resets the clock domain.

The dynamic memory clock domain controls the memory interface logic of the DMC. The input signal dmc_mclk and its inverse dmc_mclkn drive this domain. Each external dynamic memory chip is driven by a gated dmc_mclk signal, these are called dmc_clk_out[1:0]. A double speed memory clock is also required because the SDRAM type is DDR. This is driven by the input signal dmc_mclkx2 and its inverse dmc_mclkx2n. The dynamic memory interface has a fed-back clock input, dmc_fbclk_in, to help with clock skews on the external pads.

The static memory clock domain controls the memory interface logic of the SMC. The input signal smc_mclk0 and its inverse smc_mclk0n drive this domain. This is the clock used for the timings of asynchronous drive signals to the NAND memory.

The memory controller supports many different options for clocking the different domains. The dynamic and static clock domains are completely independent and have clocking options:

Dynamic memory clocking options

Table 2.1 lists the dynamic memory clocking options.

Table 2.1. Dynamic memory clocking options

OptionsTie-off values
Fully synchronous
hclk = dmc_mclk

dmc_async = dmc_msync = 1

dmc_a_gt_m_sync = 0

Synchronous multiples

hclk = n x dmc_mclk

where:

n = integer value

dmc_async = dmc_msync = 1

dmc_a_gt_m_sync = 0

m x hclk = dmc_mclk

where:

m = integer value

dmc_async = dmc_msync = 1

dmc_a_gt_m_sync = 1

Asynchronous
Extra registers are used to avoid metastability when crossing the asynchronous clock boundary.

dmc_async = dmc_msync = 0

dmc_a_gt_m_sync = 0

Static memory clocking options

Table 2.2 lists the static memory clocking options.

Table 2.2. Static memory clocking options

OptionsTie-off values
Fully synchronous
hclk = smc_mclk

smc_async0 = smc_msync0 = 1

smc_a_gt_m0_sync = 0

Synchronous multiples

hclk = n x smc_mclk0

where:

n = integer value

smc_async0 = smc_msync0 = 1

smc_a_gt_m0_sync = 0

m x hclk = smc_mclk0

where:

m = integer value

smc_async0 = smc_msync0 = 1

smc_a_gt_m0_sync = 1

Asynchronous
Extra registers are used to avoid metastability when crossing the asynchronous clock boundary.

smc_async0 = smc_msync0 = 0

smc_a_gt_m0_sync = 0

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