2.5.2. Miscellaneous signals

You can use the following signals as general-purpose control signals for logic external to the DMC:

dmc_user_status[7:0]

General-purpose ports that are readable from the APB interface. If you do not require these ports, you must tie them either HIGH or LOW. These ports are connected directly to the APB interface block. Therefore, if they are driven from external logic that is not clocked by the dmc_aclk signal, then external synchronization registers are required.

dmc_user_config[7:0]

General-purpose ports that are driven directly from a write-only APB register. If you do not require these ports leave them unconnected.

You can use the following miscellaneous signals as tie-offs to change the operational behavior of the DMC:

dmc_cke_init

The dmc_cke output port to the external memory resets to this value.

dmc_dqm_init

The dmc_dqm output ports to the external memory reset to this value.

dmc_memory_width[1:0]

This configures the external memory width. See Table 3.2 for the definition of these two pins.

dmc_msync

When HIGH, indicates dmc_mclk is synchronous to dmc_aclk. Otherwise they are asynchronous. Ensure that dmc_msync is tied to the same value as dmc_async.

dmc_async

When HIGH, indicates dmc_aclk is synchronous to dmc_mclk. Otherwise they are asynchronous. Ensure that dmc_async is tied to the same value as dmc_msync.

dmc_a_gt_m_sync

When HIGH, indicates dmc_aclk is synchronous to dmc_mclk and dmc_aclk is greater than dmc_mclk.

dmc_use_ebi

When HIGH, indicates that the DMC must operate with a PrimeCell EBI. See ARM PrimeCell External Bus Interface (PL220) Technical Reference Manual.

dmc_rst_bypass

Use this signal for ATPG testing only. It must be tied LOW for normal operation.

dmc_dft_en_clk_out

Use this signal for ATPG testing only. It must be tied LOW for normal operation.

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