2.5.1. Clocking and resets

This section describes:

Clocking

The DMC has the following functional clock inputs:

  • dmc_aclk

  • dmc_mclk

  • dmc_mclkn

  • dmc_mclkx2

  • dmc_mclkx2n

  • dmc_fbclk_in

  • dmc_dqs_in_<0-1>

  • dmc_dqs_in_n_<0-1>.

These clocks can be grouped into two clock domains:

dmc_aclk domain

dmc_aclk is in this domain. The dmc_aclk domain signals can only be stopped if the external memories are put in Self-refresh mode.

dmc_mclk domain

All clocks except dmc_aclk are in this domain. The dmc_mclk signal must be clocked at the rate of the external memory clock. The dmc_mclk domain signals can only be stopped if the external memories are put in Self-refresh mode. The dmc_mclkx2 is the double speed clock required for DDR.

You can tie off the DMC dmc_async and dmc_msync pins so that the two clock domains can operate synchronously or asynchronously with respect to each other:

Synchronous clocking

The benefit of synchronous clocking is that you can reduce the read and write latency by removing the synchronization registers between clock domains. However, because of the integer relationship of the clocks, you might not be able to get the maximum performance from the system because of constraints placed on the bus frequency by the external memory clock speed. In synchronous mode, the handshaking between the dmc_aclk and dmc_mclk domains enables synchronous operation of the two clocks at multiples of each other, that is ratios of n:1 and 1:m.

Asynchronous clocking

The main benefit of asynchronous clocking is that you can maximize the system performance, while running the memory interface at a fixed system frequency. Additionally, in sleep-mode situations when the system is not required to do much work, you can lower the frequency to reduce power consumption.

Output clocks

A clock output is provided for every external memory device. These are called dmc_clk_out[3:0]. These outputs are gated versions of the input dmc_mclk.

Data clocks

The data is clocked into and out of the external memory device using the dmc_dqs strobes. There is a strobe per external memory data byte. The strobes drive a tristate bus for write the memory controller drives out the strobes using dmc_dqs_out_<0-1>. For reads, the memory drives the strobes dmc_dqs_in_<0-1> and their inverse dmc_dqs_in_n_<0-1>.

Resets

The DMC has two reset inputs:

hresetn

This is the reset signal for the dmc_aclk domain.

dmc_mresetn

This is the reset signal for the dmc_mclk domain.

Both reset signals can be changed asynchronously to their respective clock domain. Internally to the DMC, the deassertion of the hresetn signal is synchronized to dmc_aclk, and the deassertion of the dmc_mresetn signal is synchronized to the dmc_mclk, dmc_mclkn, dmc_mckx2 and dmc_mclkx2n clock signals.

The clock inputs, dmc_fbclk, dmc_dqs_in_<0-1>, and dmc_dqs_in_n_<0-1> do not clock any resettable logic.

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